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289dd9f072
Some device may enable CONFIG_CLK but not still support this clock in CC, so better use debug() in place of dev_warn() otherwise a lot of boards will throw useless dev_warn()s. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Simon Glass <sjg@chromium.org>
571 lines
13 KiB
C
571 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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* Copyright 2013 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <fsl_lpuart.h>
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#include <watchdog.h>
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#include <asm/io.h>
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#include <serial.h>
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#include <dm/device_compat.h>
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#include <linux/compiler.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#define US1_TDRE (1 << 7)
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#define US1_RDRF (1 << 5)
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#define US1_OR (1 << 3)
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#define UC2_TE (1 << 3)
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#define UC2_RE (1 << 2)
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#define CFIFO_TXFLUSH (1 << 7)
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#define CFIFO_RXFLUSH (1 << 6)
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#define SFIFO_RXOF (1 << 2)
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#define SFIFO_RXUF (1 << 0)
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#define STAT_LBKDIF (1 << 31)
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#define STAT_RXEDGIF (1 << 30)
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#define STAT_TDRE (1 << 23)
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#define STAT_RDRF (1 << 21)
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#define STAT_IDLE (1 << 20)
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#define STAT_OR (1 << 19)
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#define STAT_NF (1 << 18)
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#define STAT_FE (1 << 17)
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#define STAT_PF (1 << 16)
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#define STAT_MA1F (1 << 15)
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#define STAT_MA2F (1 << 14)
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#define STAT_FLAGS (STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \
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STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F)
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#define CTRL_TE (1 << 19)
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#define CTRL_RE (1 << 18)
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#define FIFO_RXFLUSH BIT(14)
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#define FIFO_TXFLUSH BIT(15)
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#define FIFO_TXSIZE_MASK 0x70
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#define FIFO_TXSIZE_OFF 4
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#define FIFO_RXSIZE_MASK 0x7
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#define FIFO_RXSIZE_OFF 0
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#define FIFO_TXFE 0x80
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#if defined(CONFIG_ARCH_IMX8) || defined(CONFIG_ARCH_IMXRT)
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#define FIFO_RXFE 0x08
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#else
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#define FIFO_RXFE 0x40
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#endif
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#define WATER_TXWATER_OFF 0
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#define WATER_RXWATER_OFF 16
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DECLARE_GLOBAL_DATA_PTR;
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#define LPUART_FLAG_REGMAP_32BIT_REG BIT(0)
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#define LPUART_FLAG_REGMAP_ENDIAN_BIG BIT(1)
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enum lpuart_devtype {
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DEV_VF610 = 1,
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DEV_LS1021A,
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DEV_MX7ULP,
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DEV_IMX8,
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DEV_IMXRT,
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};
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struct lpuart_serial_platdata {
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void *reg;
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enum lpuart_devtype devtype;
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ulong flags;
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};
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static void lpuart_read32(u32 flags, u32 *addr, u32 *val)
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{
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if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
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if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
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*(u32 *)val = in_be32(addr);
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else
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*(u32 *)val = in_le32(addr);
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}
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}
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static void lpuart_write32(u32 flags, u32 *addr, u32 val)
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{
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if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
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if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
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out_be32(addr, val);
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else
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out_le32(addr, val);
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}
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}
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#ifndef CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_CLK_FREQ 0
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#endif
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u32 __weak get_lpuart_clk(void)
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{
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return CONFIG_SYS_CLK_FREQ;
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}
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#if CONFIG_IS_ENABLED(CLK)
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static int get_lpuart_clk_rate(struct udevice *dev, u32 *clk)
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{
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struct clk per_clk;
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ulong rate;
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int ret;
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ret = clk_get_by_name(dev, "per", &per_clk);
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if (ret) {
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dev_err(dev, "Failed to get per clk: %d\n", ret);
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return ret;
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}
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rate = clk_get_rate(&per_clk);
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if ((long)rate <= 0) {
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dev_err(dev, "Failed to get per clk rate: %ld\n", (long)rate);
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return ret;
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}
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*clk = rate;
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return 0;
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}
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#else
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static inline int get_lpuart_clk_rate(struct udevice *dev, u32 *clk)
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{ return -ENOSYS; }
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#endif
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static bool is_lpuart32(struct udevice *dev)
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{
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struct lpuart_serial_platdata *plat = dev->platdata;
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return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG;
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}
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static void _lpuart_serial_setbrg(struct udevice *dev,
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int baudrate)
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{
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struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
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struct lpuart_fsl *base = plat->reg;
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u32 clk;
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u16 sbr;
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int ret;
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if (CONFIG_IS_ENABLED(CLK)) {
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ret = get_lpuart_clk_rate(dev, &clk);
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if (ret)
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return;
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} else {
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clk = get_lpuart_clk();
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}
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sbr = (u16)(clk / (16 * baudrate));
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/* place adjustment later - n/32 BRFA */
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__raw_writeb(sbr >> 8, &base->ubdh);
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__raw_writeb(sbr & 0xff, &base->ubdl);
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}
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static int _lpuart_serial_getc(struct lpuart_serial_platdata *plat)
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{
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struct lpuart_fsl *base = plat->reg;
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while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
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WATCHDOG_RESET();
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barrier();
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return __raw_readb(&base->ud);
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}
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static void _lpuart_serial_putc(struct lpuart_serial_platdata *plat,
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const char c)
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{
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struct lpuart_fsl *base = plat->reg;
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while (!(__raw_readb(&base->us1) & US1_TDRE))
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WATCHDOG_RESET();
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__raw_writeb(c, &base->ud);
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}
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/* Test whether a character is in the RX buffer */
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static int _lpuart_serial_tstc(struct lpuart_serial_platdata *plat)
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{
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struct lpuart_fsl *base = plat->reg;
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if (__raw_readb(&base->urcfifo) == 0)
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return 0;
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return 1;
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}
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/*
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* Initialise the serial port with the given baudrate. The settings
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* are always 8 data bits, no parity, 1 stop bit, no start bits.
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*/
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static int _lpuart_serial_init(struct udevice *dev)
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{
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struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
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struct lpuart_fsl *base = (struct lpuart_fsl *)plat->reg;
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u8 ctrl;
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ctrl = __raw_readb(&base->uc2);
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ctrl &= ~UC2_RE;
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ctrl &= ~UC2_TE;
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__raw_writeb(ctrl, &base->uc2);
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__raw_writeb(0, &base->umodem);
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__raw_writeb(0, &base->uc1);
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/* Disable FIFO and flush buffer */
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__raw_writeb(0x0, &base->upfifo);
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__raw_writeb(0x0, &base->utwfifo);
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__raw_writeb(0x1, &base->urwfifo);
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__raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);
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/* provide data bits, parity, stop bit, etc */
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_lpuart_serial_setbrg(dev, gd->baudrate);
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__raw_writeb(UC2_RE | UC2_TE, &base->uc2);
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return 0;
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}
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static void _lpuart32_serial_setbrg_7ulp(struct udevice *dev,
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int baudrate)
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{
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struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
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struct lpuart_fsl_reg32 *base = plat->reg;
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u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
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u32 clk;
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int ret;
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if (CONFIG_IS_ENABLED(CLK)) {
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ret = get_lpuart_clk_rate(dev, &clk);
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if (ret)
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return;
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} else {
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clk = get_lpuart_clk();
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}
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baud_diff = baudrate;
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osr = 0;
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sbr = 0;
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for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
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tmp_sbr = (clk / (baudrate * tmp_osr));
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if (tmp_sbr == 0)
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tmp_sbr = 1;
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/*calculate difference in actual buad w/ current values */
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tmp_diff = (clk / (tmp_osr * tmp_sbr));
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tmp_diff = tmp_diff - baudrate;
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/* select best values between sbr and sbr+1 */
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if (tmp_diff > (baudrate - (clk / (tmp_osr * (tmp_sbr + 1))))) {
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tmp_diff = baudrate - (clk / (tmp_osr * (tmp_sbr + 1)));
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tmp_sbr++;
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}
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if (tmp_diff <= baud_diff) {
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baud_diff = tmp_diff;
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osr = tmp_osr;
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sbr = tmp_sbr;
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}
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}
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/*
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* TODO: handle buadrate outside acceptable rate
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* if (baudDiff > ((config->baudRate_Bps / 100) * 3))
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* {
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* Unacceptable baud rate difference of more than 3%
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* return kStatus_LPUART_BaudrateNotSupport;
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* }
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*/
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tmp = in_le32(&base->baud);
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if ((osr > 3) && (osr < 8))
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tmp |= LPUART_BAUD_BOTHEDGE_MASK;
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tmp &= ~LPUART_BAUD_OSR_MASK;
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tmp |= LPUART_BAUD_OSR(osr-1);
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tmp &= ~LPUART_BAUD_SBR_MASK;
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tmp |= LPUART_BAUD_SBR(sbr);
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/* explicitly disable 10 bit mode & set 1 stop bit */
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tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK);
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out_le32(&base->baud, tmp);
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}
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static void _lpuart32_serial_setbrg(struct udevice *dev,
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int baudrate)
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{
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struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
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struct lpuart_fsl_reg32 *base = plat->reg;
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u32 clk;
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u32 sbr;
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int ret;
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if (CONFIG_IS_ENABLED(CLK)) {
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ret = get_lpuart_clk_rate(dev, &clk);
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if (ret)
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return;
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} else {
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clk = get_lpuart_clk();
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}
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sbr = (clk / (16 * baudrate));
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/* place adjustment later - n/32 BRFA */
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lpuart_write32(plat->flags, &base->baud, sbr);
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}
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static int _lpuart32_serial_getc(struct lpuart_serial_platdata *plat)
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{
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struct lpuart_fsl_reg32 *base = plat->reg;
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u32 stat, val;
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lpuart_read32(plat->flags, &base->stat, &stat);
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while ((stat & STAT_RDRF) == 0) {
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lpuart_write32(plat->flags, &base->stat, STAT_FLAGS);
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WATCHDOG_RESET();
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lpuart_read32(plat->flags, &base->stat, &stat);
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}
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lpuart_read32(plat->flags, &base->data, &val);
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lpuart_read32(plat->flags, &base->stat, &stat);
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if (stat & STAT_OR)
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lpuart_write32(plat->flags, &base->stat, STAT_OR);
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return val & 0x3ff;
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}
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static void _lpuart32_serial_putc(struct lpuart_serial_platdata *plat,
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const char c)
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{
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struct lpuart_fsl_reg32 *base = plat->reg;
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u32 stat;
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if (c == '\n')
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serial_putc('\r');
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while (true) {
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lpuart_read32(plat->flags, &base->stat, &stat);
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if ((stat & STAT_TDRE))
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break;
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WATCHDOG_RESET();
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}
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lpuart_write32(plat->flags, &base->data, c);
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}
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/* Test whether a character is in the RX buffer */
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static int _lpuart32_serial_tstc(struct lpuart_serial_platdata *plat)
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{
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struct lpuart_fsl_reg32 *base = plat->reg;
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u32 water;
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lpuart_read32(plat->flags, &base->water, &water);
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if ((water >> 24) == 0)
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return 0;
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return 1;
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}
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/*
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* Initialise the serial port with the given baudrate. The settings
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* are always 8 data bits, no parity, 1 stop bit, no start bits.
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*/
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static int _lpuart32_serial_init(struct udevice *dev)
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{
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struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
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struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg;
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u32 val, tx_fifo_size;
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lpuart_read32(plat->flags, &base->ctrl, &val);
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val &= ~CTRL_RE;
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val &= ~CTRL_TE;
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lpuart_write32(plat->flags, &base->ctrl, val);
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lpuart_write32(plat->flags, &base->modir, 0);
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lpuart_read32(plat->flags, &base->fifo, &val);
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tx_fifo_size = (val & FIFO_TXSIZE_MASK) >> FIFO_TXSIZE_OFF;
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/* Set the TX water to half of FIFO size */
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if (tx_fifo_size > 1)
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tx_fifo_size = tx_fifo_size >> 1;
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/* Set RX water to 0, to be triggered by any receive data */
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lpuart_write32(plat->flags, &base->water,
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(tx_fifo_size << WATER_TXWATER_OFF));
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/* Enable TX and RX FIFO */
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val |= (FIFO_TXFE | FIFO_RXFE | FIFO_TXFLUSH | FIFO_RXFLUSH);
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lpuart_write32(plat->flags, &base->fifo, val);
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lpuart_write32(plat->flags, &base->match, 0);
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if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8 ||
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plat->devtype == DEV_IMXRT) {
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_lpuart32_serial_setbrg_7ulp(dev, gd->baudrate);
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} else {
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/* provide data bits, parity, stop bit, etc */
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_lpuart32_serial_setbrg(dev, gd->baudrate);
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}
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lpuart_write32(plat->flags, &base->ctrl, CTRL_RE | CTRL_TE);
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return 0;
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}
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static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
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{
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struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
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if (is_lpuart32(dev)) {
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if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8 ||
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plat->devtype == DEV_IMXRT)
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_lpuart32_serial_setbrg_7ulp(dev, baudrate);
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else
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_lpuart32_serial_setbrg(dev, baudrate);
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} else {
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_lpuart_serial_setbrg(dev, baudrate);
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}
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return 0;
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}
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static int lpuart_serial_getc(struct udevice *dev)
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{
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struct lpuart_serial_platdata *plat = dev->platdata;
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if (is_lpuart32(dev))
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return _lpuart32_serial_getc(plat);
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return _lpuart_serial_getc(plat);
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}
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static int lpuart_serial_putc(struct udevice *dev, const char c)
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{
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struct lpuart_serial_platdata *plat = dev->platdata;
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if (is_lpuart32(dev))
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_lpuart32_serial_putc(plat, c);
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else
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_lpuart_serial_putc(plat, c);
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return 0;
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}
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static int lpuart_serial_pending(struct udevice *dev, bool input)
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{
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struct lpuart_serial_platdata *plat = dev->platdata;
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struct lpuart_fsl *reg = plat->reg;
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struct lpuart_fsl_reg32 *reg32 = plat->reg;
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u32 stat;
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if (is_lpuart32(dev)) {
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if (input) {
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return _lpuart32_serial_tstc(plat);
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} else {
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lpuart_read32(plat->flags, ®32->stat, &stat);
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return stat & STAT_TDRE ? 0 : 1;
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}
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}
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if (input)
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return _lpuart_serial_tstc(plat);
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else
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return __raw_readb(®->us1) & US1_TDRE ? 0 : 1;
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}
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static int lpuart_serial_probe(struct udevice *dev)
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{
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#if CONFIG_IS_ENABLED(CLK)
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struct clk per_clk;
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int ret;
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ret = clk_get_by_name(dev, "per", &per_clk);
|
|
if (!ret) {
|
|
ret = clk_enable(&per_clk);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to get per clk: %d\n", ret);
|
|
return ret;
|
|
}
|
|
} else {
|
|
debug("%s: Failed to get per clk: %d\n", __func__, ret);
|
|
}
|
|
#endif
|
|
|
|
if (is_lpuart32(dev))
|
|
return _lpuart32_serial_init(dev);
|
|
else
|
|
return _lpuart_serial_init(dev);
|
|
}
|
|
|
|
static int lpuart_serial_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct lpuart_serial_platdata *plat = dev->platdata;
|
|
const void *blob = gd->fdt_blob;
|
|
int node = dev_of_offset(dev);
|
|
fdt_addr_t addr;
|
|
|
|
addr = devfdt_get_addr(dev);
|
|
if (addr == FDT_ADDR_T_NONE)
|
|
return -EINVAL;
|
|
|
|
plat->reg = (void *)addr;
|
|
plat->flags = dev_get_driver_data(dev);
|
|
|
|
if (fdtdec_get_bool(blob, node, "little-endian"))
|
|
plat->flags &= ~LPUART_FLAG_REGMAP_ENDIAN_BIG;
|
|
|
|
if (!fdt_node_check_compatible(blob, node, "fsl,ls1021a-lpuart"))
|
|
plat->devtype = DEV_LS1021A;
|
|
else if (!fdt_node_check_compatible(blob, node, "fsl,imx7ulp-lpuart"))
|
|
plat->devtype = DEV_MX7ULP;
|
|
else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart"))
|
|
plat->devtype = DEV_VF610;
|
|
else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart"))
|
|
plat->devtype = DEV_IMX8;
|
|
else if (!fdt_node_check_compatible(blob, node, "fsl,imxrt-lpuart"))
|
|
plat->devtype = DEV_IMXRT;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dm_serial_ops lpuart_serial_ops = {
|
|
.putc = lpuart_serial_putc,
|
|
.pending = lpuart_serial_pending,
|
|
.getc = lpuart_serial_getc,
|
|
.setbrg = lpuart_serial_setbrg,
|
|
};
|
|
|
|
static const struct udevice_id lpuart_serial_ids[] = {
|
|
{ .compatible = "fsl,ls1021a-lpuart", .data =
|
|
LPUART_FLAG_REGMAP_32BIT_REG | LPUART_FLAG_REGMAP_ENDIAN_BIG },
|
|
{ .compatible = "fsl,imx7ulp-lpuart",
|
|
.data = LPUART_FLAG_REGMAP_32BIT_REG },
|
|
{ .compatible = "fsl,vf610-lpuart"},
|
|
{ .compatible = "fsl,imx8qm-lpuart",
|
|
.data = LPUART_FLAG_REGMAP_32BIT_REG },
|
|
{ .compatible = "fsl,imxrt-lpuart",
|
|
.data = LPUART_FLAG_REGMAP_32BIT_REG },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(serial_lpuart) = {
|
|
.name = "serial_lpuart",
|
|
.id = UCLASS_SERIAL,
|
|
.of_match = lpuart_serial_ids,
|
|
.ofdata_to_platdata = lpuart_serial_ofdata_to_platdata,
|
|
.platdata_auto_alloc_size = sizeof(struct lpuart_serial_platdata),
|
|
.probe = lpuart_serial_probe,
|
|
.ops = &lpuart_serial_ops,
|
|
};
|