mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 18:59:44 +00:00
3f33bd299f
Fix ULPI reset polarity which caused a hard hang on Colibri T20 upon attempting to start the USB subsystem: This fixes my late commitd5a24d8b53(colibri_t20: fix usb operation and controller order) inadvertently having overwritten Stephen's previous commit2f6a7e8ce5(ARM: tegra: fix USB ULPI PHY reset signal inversion confusion). While at it also fix comment about on-module USB port. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
164 lines
3.1 KiB
Text
164 lines
3.1 KiB
Text
/dts-v1/;
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#include "tegra20.dtsi"
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/ {
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model = "Toradex Colibri T20";
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compatible = "toradex,colibri_t20", "nvidia,tegra20";
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chosen {
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stdout-path = &uarta;
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};
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aliases {
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i2c0 = "/i2c@7000d000";
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i2c1 = "/i2c@7000c000";
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i2c2 = "/i2c@7000c400";
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mmc0 = "/sdhci@c8000600";
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usb0 = "/usb@c5000000";
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usb1 = "/usb@c5004000"; /* On-module only, for ASIX */
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usb2 = "/usb@c5008000";
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};
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host1x@50000000 {
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dc@54200000 {
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rgb {
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status = "okay";
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nvidia,panel = <&lcd_panel>;
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display-timings {
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timing@0 {
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/* VESA VGA */
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clock-frequency = <25175000>;
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hactive = <640>;
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vactive = <480>;
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hback-porch = <48>;
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hfront-porch = <16>;
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hsync-len = <96>;
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vback-porch = <31>;
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vfront-porch = <11>;
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vsync-len = <2>;
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};
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};
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};
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};
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};
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nand-controller@70008000 {
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nvidia,wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
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nvidia,width = <8>;
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nvidia,timing = <15 100 25 80 25 10 15 10 100>;
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nand@0 {
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reg = <0>;
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compatible = "nand-flash";
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};
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};
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pwm@7000a000 {
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status = "okay";
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};
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/*
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* GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
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* board)
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*/
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i2c@7000c000 {
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status = "okay";
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clock-frequency = <100000>;
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};
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/* GEN2_I2C: unused */
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/* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */
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i2c@7000c400 {
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status = "okay";
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clock-frequency = <100000>;
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};
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/*
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* PWR_I2C: power I2C to PMIC and temperature sensor
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*/
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i2c@7000d000 {
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status = "okay";
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clock-frequency = <100000>;
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};
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/* EHCI instance 0: USB1_DP/N -> USBC_P/N */
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usb@c5000000 {
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status = "okay";
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dr_mode = "otg";
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};
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/* EHCI instance 1: ULPI -> USB3340 -> AX88772B */
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usb@c5004000 {
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status = "okay";
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/* ULPI_RESET */
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nvidia,phy-reset-gpio =
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<&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
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/* VBUS_LAN */
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nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
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};
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/* EHCI instance 2: USB3_DP/N -> USBH_P/N */
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usb@c5008000 {
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status = "okay";
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/* USBH_PEN */
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nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
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};
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sdhci@c8000600 {
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status = "okay";
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bus-width = <4>;
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cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
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};
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backlight: backlight {
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compatible = "pwm-backlight";
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brightness-levels = <255 128 64 32 16 8 4 0>;
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default-brightness-level = <6>;
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/* BL_ON */
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enable-gpios = <&gpio TEGRA_GPIO(T, 4) GPIO_ACTIVE_HIGH>;
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power-supply = <®_3v3>;
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/* PWM<A> */
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pwms = <&pwm 0 5000000>;
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};
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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clk32k_in: clock@0 {
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compatible = "fixed-clock";
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reg=<0>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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lcd_panel: panel {
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/*
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* edt,et057090dhu: EDT 5.7" LCD TFT
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* edt,et070080dh6: EDT 7.0" LCD TFT
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*/
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compatible = "edt,et057090dhu", "simple-panel";
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backlight = <&backlight>;
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_3v3: regulator@0 {
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compatible = "regulator-fixed";
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reg = <0>;
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regulator-name = "+V3.3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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};
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};
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