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448e2b6327
The event framework is just that, a framework. Enabling it by itself does nothing, so we shouldn't ask the user about it. Reword (and correct typos) around this the option and help text. This also applies to DM_EVENT and EVENT_DYNAMIC. Only EVENT_DEBUG and CMD_EVENT should be visible to the user to select, when EVENT is selected. With this, it's time to address the larger problems. When functionality uses events, typically via EVENT_SPY, the appropriate framework then must be select'd and NOT imply'd. As the functionality will cease to work (and so, platforms will fail to boot) this is non-optional and where select is appropriate. Audit the current users of EVENT_SPY to have a more fine-grained approach to select'ing the framework where used. Also ensure the current users of event_register and also select EVENT_DYNAMIC. Cc: AKASHI Takahiro <takahiro.akashi@linaro.org> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Reported-by: Oliver Graute <Oliver.Graute@kococonnector.com> Reported-by: Francesco Dolcini <francesco.dolcini@toradex.com> Fixes:7fe32b3442("event: Convert arch_cpu_init_dm() to use events") Fixes:42fdcebf85("event: Convert misc_init_f() to use events") Fixes:c5ef202557("dm: fix DM_EVENT dependencies") Signed-off-by: Tom Rini <trini@konsulko.com> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Fabio Estevam <festevam@denx.de>
43 lines
659 B
Text
43 lines
659 B
Text
# SPDX-License-Identifier: GPL-2.0
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#
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# Copyright (C) 2016 Google Inc.
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#
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config INTEL_BROADWELL
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bool
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select CACHE_MRC_BIN
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select DM_EVENT
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select ARCH_EARLY_INIT_R
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imply HAVE_INTEL_ME
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imply ENABLE_MRC_CACHE
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imply AHCI_PCI
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imply ICH_SPI
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imply INTEL_BROADWELL_GPIO
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imply SCSI
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imply SCSI_AHCI
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imply SPI_FLASH
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imply USB
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imply USB_EHCI_HCD
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imply VIDEO_BROADWELL_IGD
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if INTEL_BROADWELL
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config DCACHE_RAM_BASE
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default 0xff7c0000
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config DCACHE_RAM_SIZE
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default 0x40000
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config DCACHE_RAM_MRC_VAR_SIZE
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default 0x30000
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select SMM_TSEG
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select X86_RAMTEST
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config SMM_TSEG_SIZE
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hex
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default 0x800000
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endif
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