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https://github.com/AsahiLinux/u-boot
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8900e2bbec
The current ae350-related defconfigs could also support newer Andes CPU IP, so modify the names of CPU from ax25 to andesv5, and board name from ax25-ae350 to ae350. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
130 lines
2.2 KiB
C
130 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2023 Andes Technology Corporation
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* Rick Chen, Andes Technology Corporation <rick@andestech.com>
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*/
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#include <asm/csr.h>
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#include <asm/asm.h>
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#include <common.h>
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#include <cache.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <dm/uclass-internal.h>
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#include <asm/arch-andes/csr.h>
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#ifdef CONFIG_V5L2_CACHE
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void enable_caches(void)
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{
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struct udevice *dev;
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int ret;
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ret = uclass_get_device_by_driver(UCLASS_CACHE,
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DM_DRIVER_GET(v5l2_cache),
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&dev);
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if (ret) {
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log_debug("Cannot enable v5l2 cache\n");
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} else {
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ret = cache_enable(dev);
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if (ret)
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log_debug("v5l2 cache enable failed\n");
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}
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}
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static void cache_ops(int (*ops)(struct udevice *dev))
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{
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struct udevice *dev = NULL;
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uclass_find_first_device(UCLASS_CACHE, &dev);
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if (dev)
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ops(dev);
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}
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#endif
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void flush_dcache_all(void)
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{
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#if CONFIG_IS_ENABLED(RISCV_MMODE)
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csr_write(CSR_MCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL);
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#endif
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}
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void flush_dcache_range(unsigned long start, unsigned long end)
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{
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flush_dcache_all();
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}
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void invalidate_dcache_range(unsigned long start, unsigned long end)
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{
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flush_dcache_all();
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}
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void icache_enable(void)
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{
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#if CONFIG_IS_ENABLED(RISCV_MMODE)
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asm volatile("csrsi %0, 0x1" :: "i"(CSR_MCACHE_CTL));
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#endif
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}
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void icache_disable(void)
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{
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#if CONFIG_IS_ENABLED(RISCV_MMODE)
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asm volatile("csrci %0, 0x1" :: "i"(CSR_MCACHE_CTL));
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#endif
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}
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void dcache_enable(void)
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{
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#if CONFIG_IS_ENABLED(RISCV_MMODE)
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asm volatile("csrsi %0, 0x2" :: "i"(CSR_MCACHE_CTL));
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#endif
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#ifdef CONFIG_V5L2_CACHE
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cache_ops(cache_enable);
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#endif
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}
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void dcache_disable(void)
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{
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#if CONFIG_IS_ENABLED(RISCV_MMODE)
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asm volatile("csrci %0, 0x2" :: "i"(CSR_MCACHE_CTL));
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#endif
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#ifdef CONFIG_V5L2_CACHE
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cache_ops(cache_disable);
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#endif
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}
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int icache_status(void)
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{
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int ret = 0;
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#if CONFIG_IS_ENABLED(RISCV_MMODE)
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asm volatile (
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"csrr t1, %1\n\t"
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"andi %0, t1, 0x01\n\t"
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: "=r" (ret)
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: "i"(CSR_MCACHE_CTL)
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: "memory"
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);
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#endif
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return !!ret;
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}
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int dcache_status(void)
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{
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int ret = 0;
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#if CONFIG_IS_ENABLED(RISCV_MMODE)
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asm volatile (
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"csrr t1, %1\n\t"
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"andi %0, t1, 0x02\n\t"
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: "=r" (ret)
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: "i" (CSR_MCACHE_CTL)
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: "memory"
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);
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#endif
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return !!ret;
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}
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