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54e75702c4
Such as rk3288's pins of pmu_gpio0 are a special feature, which have no higher 16 writing corresponding bits, use common set_mux() func would introduce more code, so implement their set_mux() in each Soc's own file to reduce the size of code. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
107 lines
2.9 KiB
C
107 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/pinctrl.h>
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#include <regmap.h>
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#include <syscon.h>
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#include "pinctrl-rockchip.h"
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static int rk3188_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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int iomux_num = (pin / 8);
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struct regmap *regmap;
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int reg, ret, mask, mux_type;
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u8 bit;
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u32 data;
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regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
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? priv->regmap_pmu : priv->regmap_base;
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/* get basic quadrupel of mux registers and the correct reg inside */
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mux_type = bank->iomux[iomux_num].type;
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reg = bank->iomux[iomux_num].offset;
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reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
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data = (mask << (bit + 16));
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data |= (mux & mask) << bit;
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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#define RK3188_PULL_OFFSET 0x164
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#define RK3188_PULL_PMU_OFFSET 0x64
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static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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/* The first 12 pins of the first bank are located elsewhere */
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if (bank->bank_num == 0 && pin_num < 12) {
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*regmap = priv->regmap_pmu;
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*reg = RK3188_PULL_PMU_OFFSET;
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*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
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*bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG;
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*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
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} else {
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*regmap = priv->regmap_base;
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*reg = RK3188_PULL_OFFSET;
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/* correct the offset, as it is the 2nd pull register */
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*reg -= 4;
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*reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
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*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
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/*
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* The bits in these registers have an inverse ordering
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* with the lowest pin being in bits 15:14 and the highest
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* pin in bits 1:0
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*/
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*bit = 7 - (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
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*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
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}
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}
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static struct rockchip_pin_bank rk3188_pin_banks[] = {
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PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
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PIN_BANK(1, 32, "gpio1"),
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PIN_BANK(2, 32, "gpio2"),
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PIN_BANK(3, 32, "gpio3"),
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};
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static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
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.pin_banks = rk3188_pin_banks,
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.nr_banks = ARRAY_SIZE(rk3188_pin_banks),
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.label = "RK3188-GPIO",
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.type = RK3188,
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.grf_mux_offset = 0x60,
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.set_mux = rk3188_set_mux,
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.pull_calc_reg = rk3188_calc_pull_reg_and_bit,
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};
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static const struct udevice_id rk3188_pinctrl_ids[] = {
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{ .compatible = "rockchip,rk3188-pinctrl",
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.data = (ulong)&rk3188_pin_ctrl },
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{ }
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};
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U_BOOT_DRIVER(pinctrl_rk3188) = {
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.name = "rockchip_rk3188_pinctrl",
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.id = UCLASS_PINCTRL,
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.of_match = rk3188_pinctrl_ids,
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.priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
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.ops = &rockchip_pinctrl_ops,
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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.bind = dm_scan_fdt_dev,
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#endif
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.probe = rockchip_pinctrl_probe,
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};
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