mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-15 07:43:07 +00:00
54a08c4139
This syncs drivers/ddr/marvell/a38x/ with the master branch of repository
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
up to the commit "mv_ddr: a3700: Use the right size for memset to not overflow"
d5acc10c287e40cc2feeb28710b92e45c93c702c
This patch was created by following steps:
1. Replace all a38x files in U-Boot tree by files from upstream github
Marvell mv-ddr-marvell repository.
2. Run following command to omit portions not relevant for a38x, ddr3, and ddr4:
files=drivers/ddr/marvell/a38x/*
unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_APN806 \
-UCONFIG_MC_STATIC -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
-UCONFIG_PHY_STATIC_PRINT -UCONFIG_CUSTOMER_BOARD_SUPPORT \
-UCONFIG_A3700 -UA3900 -UA80X0 -UA70X0 -DCONFIG_ARMADA_38X -UCONFIG_ARMADA_39X \
-UCONFIG_64BIT $files
3. Manually change license to SPDX-License-Identifier
(upstream license in upstream github repository contains long license
texts and U-Boot is using just SPDX-License-Identifier.
After applying this patch, a38x, ddr3, and ddr4 code in upstream Marvell github
repository and in U-Boot would be fully identical. So in future applying
above steps could be used to sync code again.
The only change in this patch are:
1. Some fixes with include files.
2. Some function return and basic type defines changes in
mv_ddr_plat.c (to correct Marvell bug).
3. Remove of dead code in newly copied files (as a result of the
filter script stripping out everything other than a38x, dd3, and ddr4).
Reference:
"ddr: marvell: a38x: Sync code with Marvell mv-ddr-marvell repository"
107c3391b9
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
131 lines
3.5 KiB
C
131 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#ifndef _DDR3_LOGGING_CONFIG_H
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#define _DDR3_LOGGING_CONFIG_H
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#ifdef SILENT_LIB
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#define DEBUG_TRAINING_BIST_ENGINE(level, s)
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#define DEBUG_TRAINING_IP(level, s)
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#define DEBUG_CENTRALIZATION_ENGINE(level, s)
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#define DEBUG_TRAINING_HW_ALG(level, s)
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#define DEBUG_TRAINING_IP_ENGINE(level, s)
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#define DEBUG_LEVELING(level, s)
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#define DEBUG_PBS_ENGINE(level, s)
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#define DEBUG_TRAINING_STATIC_IP(level, s)
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#define DEBUG_TRAINING_ACCESS(level, s)
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#else
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#ifdef LIB_FUNCTIONAL_DEBUG_ONLY
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#define DEBUG_TRAINING_BIST_ENGINE(level, s)
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#define DEBUG_TRAINING_IP_ENGINE(level, s)
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#define DEBUG_TRAINING_IP(level, s) \
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if (level >= debug_training) \
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printf s
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#define DEBUG_CENTRALIZATION_ENGINE(level, s) \
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if (level >= debug_centralization) \
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printf s
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#define DEBUG_TRAINING_HW_ALG(level, s) \
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if (level >= debug_training_hw_alg) \
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printf s
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#define DEBUG_LEVELING(level, s) \
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if (level >= debug_leveling) \
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printf s
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#define DEBUG_PBS_ENGINE(level, s) \
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if (level >= debug_pbs) \
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printf s
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#define DEBUG_TRAINING_STATIC_IP(level, s) \
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if (level >= debug_training_static) \
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printf s
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#define DEBUG_TRAINING_ACCESS(level, s) \
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if (level >= debug_training_access) \
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printf s
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#else
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#define DEBUG_TRAINING_BIST_ENGINE(level, s) \
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if (level >= debug_training_bist) \
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printf s
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#define DEBUG_TRAINING_IP_ENGINE(level, s) \
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if (level >= debug_training_ip) \
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printf s
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#define DEBUG_TRAINING_IP(level, s) \
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if (level >= debug_training) \
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printf s
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#define DEBUG_CENTRALIZATION_ENGINE(level, s) \
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if (level >= debug_centralization) \
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printf s
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#define DEBUG_TRAINING_HW_ALG(level, s) \
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if (level >= debug_training_hw_alg) \
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printf s
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#define DEBUG_LEVELING(level, s) \
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if (level >= debug_leveling) \
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printf s
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#define DEBUG_PBS_ENGINE(level, s) \
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if (level >= debug_pbs) \
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printf s
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#define DEBUG_TRAINING_STATIC_IP(level, s) \
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if (level >= debug_training_static) \
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printf s
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#define DEBUG_TRAINING_ACCESS(level, s) \
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if (level >= debug_training_access) \
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printf s
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#endif
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#endif
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#ifdef CONFIG_DDR4
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#ifdef SILENT_LIB
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#define DEBUG_TAP_TUNING_ENGINE(level, s)
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#define DEBUG_CALIBRATION(level, s)
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#define DEBUG_DDR4_CENTRALIZATION(level, s)
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#define DEBUG_DM_TUNING(level, s)
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#else /* SILENT_LIB */
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#define DEBUG_TAP_TUNING_ENGINE(level, s) \
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if (level >= debug_tap_tuning) \
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printf s
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#define DEBUG_CALIBRATION(level, s) \
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if (level >= debug_calibration) \
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printf s
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#define DEBUG_DDR4_CENTRALIZATION(level, s) \
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if (level >= debug_ddr4_centralization) \
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printf s
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#define DEBUG_DM_TUNING(level, s) \
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if (level >= debug_dm_tuning) \
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printf s
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#endif /* SILENT_LIB */
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#endif /* CONFIG_DDR4 */
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/* Logging defines */
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enum mv_ddr_debug_level {
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DEBUG_LEVEL_TRACE = 1,
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DEBUG_LEVEL_INFO = 2,
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DEBUG_LEVEL_ERROR = 3,
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DEBUG_LEVEL_LAST
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};
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enum ddr_lib_debug_block {
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DEBUG_BLOCK_STATIC,
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DEBUG_BLOCK_TRAINING_MAIN,
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DEBUG_BLOCK_LEVELING,
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DEBUG_BLOCK_CENTRALIZATION,
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DEBUG_BLOCK_PBS,
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DEBUG_BLOCK_IP,
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DEBUG_BLOCK_BIST,
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DEBUG_BLOCK_ALG,
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DEBUG_BLOCK_DEVICE,
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DEBUG_BLOCK_ACCESS,
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DEBUG_STAGES_REG_DUMP,
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#if defined(CONFIG_DDR4)
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DEBUG_TAP_TUNING_ENGINE,
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DEBUG_BLOCK_CALIBRATION,
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DEBUG_BLOCK_DDR4_CENTRALIZATION,
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DEBUG_DM_TUNING,
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#endif /* CONFIG_DDR4 */
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/* All excluding IP and REG_DUMP, should be enabled separatelly */
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DEBUG_BLOCK_ALL
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};
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int ddr3_tip_print_log(u32 dev_num, u32 mem_addr);
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int ddr3_tip_print_stability_log(u32 dev_num);
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#endif /* _DDR3_LOGGING_CONFIG_H */
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