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https://github.com/AsahiLinux/u-boot
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a187559e3d
Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
208 lines
5 KiB
C
208 lines
5 KiB
C
/*
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* U-Boot - blackfin_local.h
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*
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* Copyright (c) 2005-2007 Analog Devices Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __BLACKFIN_LOCAL_H__
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#define __BLACKFIN_LOCAL_H__
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#include <asm/mem_map.h>
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#define LO(con32) ((con32) & 0xFFFF)
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#define lo(con32) ((con32) & 0xFFFF)
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#define HI(con32) (((con32) >> 16) & 0xFFFF)
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#define hi(con32) (((con32) >> 16) & 0xFFFF)
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#define OFFSET_(x) (x & 0x0000FFFF)
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#define MK_BMSK_(x) (1 << x)
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/* Ideally this should be USEC not MSEC, but the USEC multiplication
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* likes to overflow 32bit quantities which is all our assembler
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* currently supports ;(
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*/
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#define USEC_PER_MSEC 1000
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#define MSEC_PER_SEC 1000
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#define BFIN_SCLK (100000000)
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#define SCLK_TO_MSEC(sclk) ((MSEC_PER_SEC * ((sclk) / USEC_PER_MSEC)) / (BFIN_SCLK / USEC_PER_MSEC))
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#define MSEC_TO_SCLK(msec) ((((BFIN_SCLK / USEC_PER_MSEC) * (msec)) / MSEC_PER_SEC) * USEC_PER_MSEC)
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#define L1_CACHE_SHIFT 5
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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#include <linux/linkage.h>
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#include <asm/cache.h>
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#ifndef __ASSEMBLY__
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# ifdef SHARED_RESOURCES
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# include <asm/shared_resources.h>
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# endif
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# include <linux/types.h>
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# define bfin_revid() (bfin_read_CHIPID() >> 28)
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extern int bfin_os_log_check(void);
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extern void bfin_os_log_dump(void);
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extern void blackfin_icache_flush_range(const void *, const void *);
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extern void blackfin_dcache_flush_range(const void *, const void *);
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extern void blackfin_icache_dcache_flush_range(const void *, const void *);
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extern void blackfin_dcache_flush_invalidate_range(const void *, const void *);
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/* Use DMA to move data from on chip to external memory. The L1 instruction
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* regions can only be accessed via DMA, so if the address in question is in
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* that region, make sure we attempt to DMA indirectly.
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*/
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# ifdef __ADSPBF561__
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/* Core B regions all need dma from Core A */
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# define addr_bfin_on_chip_mem(addr) \
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((((unsigned long)(addr) & 0xFFF00000) == 0xFFA00000) || \
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(((unsigned long)(addr) & 0xFFC00000) == 0xFF400000))
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# else
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# define addr_bfin_on_chip_mem(addr) \
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(((unsigned long)(addr) & 0xFFF00000) == 0xFFA00000)
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# endif
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# include <asm/system.h>
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#if ANOMALY_05000198
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# define NOP_PAD_ANOMALY_05000198 "nop;"
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#else
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# define NOP_PAD_ANOMALY_05000198
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#endif
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#define BFIN_BUG() while (1) asm volatile("emuexcpt;");
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#define _bfin_readX(addr, size, asm_size, asm_ext) ({ \
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u32 __v; \
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__asm__ __volatile__( \
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NOP_PAD_ANOMALY_05000198 \
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"%0 = " #asm_size "[%1]" #asm_ext ";" \
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: "=d" (__v) \
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: "a" (addr) \
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); \
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__v; })
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#define _bfin_writeX(addr, val, size, asm_size) \
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__asm__ __volatile__( \
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NOP_PAD_ANOMALY_05000198 \
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#asm_size "[%0] = %1;" \
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: \
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: "a" (addr), "d" ((u##size)(val)) \
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: "memory" \
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)
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#define bfin_read8(addr) _bfin_readX(addr, 8, b, (z))
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#define bfin_read16(addr) _bfin_readX(addr, 16, w, (z))
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#define bfin_read32(addr) _bfin_readX(addr, 32, , )
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#define bfin_write8(addr, val) _bfin_writeX(addr, val, 8, b)
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#define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w)
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#define bfin_write32(addr, val) _bfin_writeX(addr, val, 32, )
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#define bfin_read(addr) \
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({ \
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sizeof(*(addr)) == 1 ? bfin_read8(addr) : \
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sizeof(*(addr)) == 2 ? bfin_read16(addr) : \
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sizeof(*(addr)) == 4 ? bfin_read32(addr) : \
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({ BFIN_BUG(); 0; }); \
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})
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#define bfin_write(addr, val) \
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do { \
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switch (sizeof(*(addr))) { \
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case 1: bfin_write8(addr, val); break; \
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case 2: bfin_write16(addr, val); break; \
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case 4: bfin_write32(addr, val); break; \
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default: \
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BFIN_BUG(); \
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} \
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} while (0)
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#define bfin_write_or(addr, bits) \
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do { \
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typeof(addr) __addr = (addr); \
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bfin_write(__addr, bfin_read(__addr) | (bits)); \
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} while (0)
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#define bfin_write_and(addr, bits) \
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do { \
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typeof(addr) __addr = (addr); \
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bfin_write(__addr, bfin_read(__addr) & (bits)); \
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} while (0)
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#define bfin_readPTR(addr) bfin_read32(addr)
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#define bfin_writePTR(addr, val) bfin_write32(addr, val)
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/* SSYNC implementation for C file */
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static inline void SSYNC(void)
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{
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int _tmp;
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if (ANOMALY_05000312)
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__asm__ __volatile__(
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"cli %0;"
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"nop;"
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"nop;"
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"ssync;"
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"sti %0;"
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: "=d" (_tmp)
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);
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else if (ANOMALY_05000244)
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__asm__ __volatile__(
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"nop;"
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"nop;"
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"nop;"
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"ssync;"
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);
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else
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__asm__ __volatile__("ssync;");
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}
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/* CSYNC implementation for C file */
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static inline void CSYNC(void)
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{
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int _tmp;
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if (ANOMALY_05000312)
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__asm__ __volatile__(
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"cli %0;"
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"nop;"
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"nop;"
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"csync;"
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"sti %0;"
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: "=d" (_tmp)
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);
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else if (ANOMALY_05000244)
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__asm__ __volatile__(
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"nop;"
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"nop;"
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"nop;"
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"csync;"
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);
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else
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__asm__ __volatile__("csync;");
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}
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#else /* __ASSEMBLY__ */
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/* SSYNC & CSYNC implementations for assembly files */
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#define ssync(x) SSYNC(x)
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#define csync(x) CSYNC(x)
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#if ANOMALY_05000312
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#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch;
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#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch;
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#elif ANOMALY_05000244
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#define SSYNC(scratch) nop; nop; nop; SSYNC;
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#define CSYNC(scratch) nop; nop; nop; CSYNC;
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#else
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#define SSYNC(scratch) SSYNC;
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#define CSYNC(scratch) CSYNC;
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#endif /* ANOMALY_05000312 & ANOMALY_05000244 handling */
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#endif /* __ASSEMBLY__ */
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#endif
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