mirror of
https://github.com/AsahiLinux/u-boot
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122 lines
3.2 KiB
C
122 lines
3.2 KiB
C
/*
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* (C) Copyright 2007
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Author: Igor Lisitsin <igor@emcraft.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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/* Cache test
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*
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* This test verifies the CPU data and instruction cache using
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* several test scenarios.
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*/
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#include <post.h>
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#if CONFIG_POST & CONFIG_SYS_POST_CACHE
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#include <asm/mmu.h>
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#include <watchdog.h>
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#define CACHE_POST_SIZE 1024
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int cache_post_test1 (int tlb, void *p, int size);
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int cache_post_test2 (int tlb, void *p, int size);
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int cache_post_test3 (int tlb, void *p, int size);
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int cache_post_test4 (int tlb, void *p, int size);
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int cache_post_test5 (int tlb, void *p, int size);
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int cache_post_test6 (int tlb, void *p, int size);
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#ifdef CONFIG_440
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static unsigned char testarea[CACHE_POST_SIZE]
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__attribute__((__aligned__(CACHE_POST_SIZE)));
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#endif
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int cache_post_test (int flags)
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{
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void *virt = (void *)CONFIG_SYS_POST_CACHE_ADDR;
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int ints;
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int res = 0;
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int tlb = -1; /* index to the victim TLB entry */
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/*
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* All 44x variants deal with cache management differently
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* because they have the address translation always enabled.
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* The 40x ppc's don't use address translation in U-Boot at all,
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* so we have to distinguish here between 40x and 44x.
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*/
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#ifdef CONFIG_440
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int word0, i;
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/*
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* Allocate a new TLB entry, since we are going to modify
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* the write-through and caching inhibited storage attributes.
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*/
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program_tlb((u32)testarea, (u32)virt, CACHE_POST_SIZE,
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TLB_WORD2_I_ENABLE);
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/* Find the TLB entry */
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for (i = 0;; i++) {
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if (i >= PPC4XX_TLB_SIZE) {
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printf ("Failed to program tlb entry\n");
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return -1;
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}
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word0 = mftlb1(i);
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if (TLB_WORD0_EPN_DECODE(word0) == (u32)virt) {
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tlb = i;
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break;
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}
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}
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#endif
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ints = disable_interrupts ();
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WATCHDOG_RESET ();
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if (res == 0)
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res = cache_post_test1 (tlb, virt, CACHE_POST_SIZE);
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WATCHDOG_RESET ();
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if (res == 0)
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res = cache_post_test2 (tlb, virt, CACHE_POST_SIZE);
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WATCHDOG_RESET ();
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if (res == 0)
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res = cache_post_test3 (tlb, virt, CACHE_POST_SIZE);
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WATCHDOG_RESET ();
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if (res == 0)
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res = cache_post_test4 (tlb, virt, CACHE_POST_SIZE);
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WATCHDOG_RESET ();
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if (res == 0)
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res = cache_post_test5 (tlb, virt, CACHE_POST_SIZE);
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WATCHDOG_RESET ();
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if (res == 0)
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res = cache_post_test6 (tlb, virt, CACHE_POST_SIZE);
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if (ints)
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enable_interrupts ();
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#ifdef CONFIG_440
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remove_tlb((u32)virt, CACHE_POST_SIZE);
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#endif
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return res;
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}
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#endif /* CONFIG_POST & CONFIG_SYS_POST_CACHE */
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