mirror of
https://github.com/AsahiLinux/u-boot
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64e8482f1c
This driver is currently responsible for enabling the clock gating feature of SiFive pre core's private L2 cache. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
44 lines
983 B
C
44 lines
983 B
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2023 SiFive
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*/
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#include <cache.h>
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#include <dm.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <dm/device.h>
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#include <dm/device-internal.h>
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#define SIFIVE_PL2CHICKENBIT_OFFSET 0x1000
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#define SIFIVE_PL2CHICKENBIT_REGIONCLOCKDISABLE_MASK BIT(3)
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static int sifive_pl2_probe(struct udevice *dev)
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{
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fdt_addr_t base;
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u32 val;
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base = dev_read_addr(dev);
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if (base == FDT_ADDR_T_NONE)
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return -EINVAL;
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/* Enable regionClockDisable bit */
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val = readl((void __iomem *)(base + SIFIVE_PL2CHICKENBIT_OFFSET));
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writel(val & ~SIFIVE_PL2CHICKENBIT_REGIONCLOCKDISABLE_MASK,
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(void __iomem *)(base + SIFIVE_PL2CHICKENBIT_OFFSET));
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return 0;
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}
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static const struct udevice_id sifive_pl2_ids[] = {
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{ .compatible = "sifive,pl2cache0" },
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{ .compatible = "sifive,pl2cache1" },
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{}
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};
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U_BOOT_DRIVER(sifive_pl2) = {
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.name = "sifive_pl2",
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.id = UCLASS_CACHE,
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.of_match = sifive_pl2_ids,
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.probe = sifive_pl2_probe,
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};
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