mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-19 03:08:31 +00:00
244 lines
6.9 KiB
C
244 lines
6.9 KiB
C
/*
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* Copyright (C) 2003 Travis B. Sawyer <travis.sawyer@sandburst.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <spd_sdram.h>
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#include <i2c.h>
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#include <net.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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unsigned long sdrreg;
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/*
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* Enable GPIO for pins 18 - 24
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* 18 = SEEPROM_WP
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* 19 = #M_RST
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* 20 = #MONARCH
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* 21 = #LED_ALARM
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* 22 = #LED_ACT
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* 23 = #LED_STATUS1
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* 24 = #LED_STATUS2
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*/
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mfsdr(sdr_pfc0, sdrreg);
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mtsdr(sdr_pfc0, (sdrreg & ~SDR0_PFC0_TRE_ENABLE) | 0x00003e00);
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out32(CONFIG_SYS_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3));
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LED0_OFF();
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LED1_OFF();
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LED2_OFF();
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LED3_OFF();
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/* Setup the external bus controller/chip selects */
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mtebc(pb0ap, 0x04055200); /* 16MB Strata FLASH */
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mtebc(pb0cr, 0xff098000); /* BAS=0xff0 16MB R/W 8-bit */
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mtebc(pb1ap, 0x04055200); /* 512KB Socketed AMD FLASH */
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mtebc(pb1cr, 0xfe018000); /* BAS=0xfe0 1MB R/W 8-bit */
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mtebc(pb6ap, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */
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mtebc(pb6cr, 0xf00da000); /* BAS=0xf00 64MB R/W i6-bit */
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mtebc(pb7ap, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */
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mtebc(pb7cr, 0xf40da000); /* BAS=0xf40 64MB R/W 16-bit */
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/*
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* Setup the interrupt controller polarities, triggers, etc.
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*
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* Because of the interrupt handling rework to handle 440GX interrupts
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* with the common code, we needed to change names of the UIC registers.
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* Here the new relationship:
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*
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* U-Boot name 440GX name
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* -----------------------
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* UIC0 UICB0
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* UIC1 UIC0
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* UIC2 UIC1
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* UIC3 UIC2
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*/
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mtdcr(uic1sr, 0xffffffff); /* clear all */
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mtdcr(uic1er, 0x00000000); /* disable all */
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mtdcr(uic1cr, 0x00000003); /* SMI & UIC1 crit are critical */
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mtdcr(uic1pr, 0xfffffe00); /* per ref-board manual */
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mtdcr(uic1tr, 0x01c00000); /* per ref-board manual */
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mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(uic1sr, 0xffffffff); /* clear all */
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mtdcr(uic2sr, 0xffffffff); /* clear all */
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mtdcr(uic2er, 0x00000000); /* disable all */
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mtdcr(uic2cr, 0x00000000); /* all non-critical */
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mtdcr(uic2pr, 0xffffc0ff); /* per ref-board manual */
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mtdcr(uic2tr, 0x00ff8000); /* per ref-board manual */
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mtdcr(uic2vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(uic2sr, 0xffffffff); /* clear all */
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mtdcr(uic3sr, 0xffffffff); /* clear all */
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mtdcr(uic3er, 0x00000000); /* disable all */
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mtdcr(uic3cr, 0x00000000); /* all non-critical */
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mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */
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mtdcr(uic3tr, 0x00ff8c0f); /* per ref-board manual */
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mtdcr(uic3vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(uic3sr, 0xffffffff); /* clear all */
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mtdcr(uic0sr, 0xfc000000); /* clear all */
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mtdcr(uic0er, 0x00000000); /* disable all */
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mtdcr(uic0cr, 0x00000000); /* all non-critical */
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mtdcr(uic0pr, 0xfc000000); /* */
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mtdcr(uic0tr, 0x00000000); /* */
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mtdcr(uic0vr, 0x00000001); /* */
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LED0_ON();
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return 0;
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}
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int checkboard(void)
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{
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char *s;
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printf("Board: X-ES %s PMC SBC\n", CONFIG_SYS_BOARD_NAME);
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printf(" ");
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s = getenv("board_rev");
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if (s)
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printf("Rev %s, ", s);
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s = getenv("serial#");
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if (s)
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printf("Serial# %s, ", s);
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s = getenv("board_cfg");
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if (s)
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printf("Cfg %s", s);
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printf("\n");
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return 0;
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}
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phys_size_t initdram(int board_type)
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{
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return spd_sdram();
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}
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/*
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* This routine is called just prior to registering the hose and gives
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* the board the opportunity to check things. Returning a value of zero
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* indicates that things are bad & PCI initialization should be aborted.
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*
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* Different boards may wish to customize the pci controller structure
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* (add regions, override default access routines, etc) or perform
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* certain pre-initialization actions.
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*/
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#if defined(CONFIG_PCI)
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int pci_pre_init(struct pci_controller * hose)
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{
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unsigned long strap;
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/* See if we're supposed to setup the pci */
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mfsdr(sdr_sdstp1, strap);
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if ((strap & 0x00010000) == 0)
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return 0;
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#if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV)
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/* Setup System Device Register PCIX0_XCR */
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mfsdr(sdr_xcr, strap);
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strap &= 0x0f000000;
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mtsdr(sdr_xcr, strap);
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#endif
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return 1;
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}
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#endif /* defined(CONFIG_PCI) */
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#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
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/*
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* The bootstrap configuration provides default settings for the pci
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* inbound map (PIM). But the bootstrap config choices are limited and
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* may not be sufficient for a given board.
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*/
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void pci_target_init(struct pci_controller * hose)
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{
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/* Disable everything */
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out32r(PCIX0_PIM0SA, 0);
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out32r(PCIX0_PIM1SA, 0);
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out32r(PCIX0_PIM2SA, 0);
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out32r(PCIX0_EROMBA, 0); /* disable expansion rom */
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/*
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* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
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* options to not support sizes such as 128/256 MB.
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*/
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out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
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out32r(PCIX0_PIM0LAH, 0);
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out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
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out32r(PCIX0_BAR0, 0);
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/* Program the board's subsystem id/vendor id */
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out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
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out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
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out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
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}
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#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
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#if defined(CONFIG_PCI)
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/*
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* This routine is called to determine if a pci scan should be
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* performed. With various hardware environments (especially cPCI and
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* PPMC) it's insufficient to depend on the state of the arbiter enable
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* bit in the strap register, or generic host/adapter assumptions.
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*
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* Rather than hard-code a bad assumption in the general 440 code, the
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* 440 pci code requires the board to decide at runtime.
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*
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* Return 0 for adapter mode, non-zero for host (monarch) mode.
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*/
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int is_pci_host(struct pci_controller *hose)
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{
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return ((in32(CONFIG_SYS_GPIO_BASE + 0x1C) & 0x00000800) == 0);
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}
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#endif /* defined(CONFIG_PCI) */
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#ifdef CONFIG_POST
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/*
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* Returns 1 if keys pressed to start the power-on long-running tests
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* Called from board_init_f().
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*/
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int post_hotkeys_pressed(void)
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{
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return ctrlc();
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}
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void post_word_store(ulong a)
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{
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volatile ulong *save_addr =
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(volatile ulong *)(CONFIG_SYS_POST_WORD_ADDR);
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*save_addr = a;
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}
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ulong post_word_load(void)
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{
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volatile ulong *save_addr =
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(volatile ulong *)(CONFIG_SYS_POST_WORD_ADDR);
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return *save_addr;
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}
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#endif
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