mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-04 02:20:25 +00:00
fb2bdc4efc
i.MX93 11x11 EVK fails to boot: U-Boot SPL 2023.10-00558-g65b9b3462bec-dirty (Oct 03 2023 - 17:40:10 +0200) SOC: 0xa0009300 LC: 0x40010 M33 prepare ok Normal Boot Trying to boot from BOOTROM Boot Stage: Primary boot image offset 0x8000, pagesize 0x200, ivt offset 0x0 Load image from 0x44400 by ROM_API NOTICE: BL31: v2.8(release):android-13.0.0_2.0.0-0-ge4b2dbfa52f5 NOTICE: BL31: Built : 17:52:46, Sep 28 2023 That's because commit9e644284ab("dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation"): "[This] changes behavior of what nodes are bound in the U-Boot proper pre-relocation phase. Change to bootph-all or add bootph-some-ram prop to restore prior behavior." Fix this by adding bootph-some-ram prop as suggested by the commit above. Fixes:9e644284ab("dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation") Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
171 lines
2.1 KiB
Text
171 lines
2.1 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright 2022 NXP
|
|
*/
|
|
|
|
/ {
|
|
wdt-reboot {
|
|
compatible = "wdt-reboot";
|
|
wdt = <&wdog3>;
|
|
bootph-pre-ram;
|
|
bootph-some-ram;
|
|
};
|
|
|
|
firmware {
|
|
optee {
|
|
compatible = "linaro,optee-tz";
|
|
method = "smc";
|
|
};
|
|
};
|
|
};
|
|
|
|
&{/soc@0} {
|
|
bootph-all;
|
|
bootph-pre-ram;
|
|
};
|
|
|
|
&aips1 {
|
|
bootph-pre-ram;
|
|
bootph-all;
|
|
};
|
|
|
|
&aips2 {
|
|
bootph-pre-ram;
|
|
bootph-some-ram;
|
|
};
|
|
|
|
&aips3 {
|
|
bootph-pre-ram;
|
|
bootph-some-ram;
|
|
};
|
|
|
|
&iomuxc {
|
|
bootph-pre-ram;
|
|
bootph-some-ram;
|
|
};
|
|
|
|
®_usdhc2_vmmc {
|
|
u-boot,off-on-delay-us = <20000>;
|
|
bootph-pre-ram;
|
|
bootph-some-ram;
|
|
};
|
|
|
|
&pinctrl_reg_usdhc2_vmmc {
|
|
bootph-pre-ram;
|
|
};
|
|
|
|
&pinctrl_uart1 {
|
|
bootph-pre-ram;
|
|
bootph-some-ram;
|
|
};
|
|
|
|
&pinctrl_usdhc2_gpio {
|
|
bootph-pre-ram;
|
|
bootph-some-ram;
|
|
};
|
|
|
|
&pinctrl_usdhc2 {
|
|
bootph-pre-ram;
|
|
bootph-some-ram;
|
|
};
|
|
|
|
&gpio1 {
|
|
bootph-pre-ram;
|
|
bootph-some-ram;
|
|
};
|
|
|
|
&gpio2 {
|
|
bootph-pre-ram;
|
|
bootph-some-ram;
|
|
};
|
|
|
|
&gpio3 {
|
|
bootph-pre-ram;
|
|
bootph-some-ram;
|
|
};
|
|
|
|
&gpio4 {
|
|
bootph-pre-ram;
|
|
bootph-some-ram;
|
|
};
|
|
|
|
&lpuart1 {
|
|
bootph-pre-ram;
|
|
bootph-some-ram;
|
|
};
|
|
|
|
&usdhc1 {
|
|
bootph-pre-ram;
|
|
bootph-some-ram;
|
|
};
|
|
|
|
&usdhc2 {
|
|
bootph-pre-ram;
|
|
bootph-some-ram;
|
|
fsl,signal-voltage-switch-extra-delay-ms = <8>;
|
|
};
|
|
|
|
&lpi2c2 {
|
|
bootph-pre-ram;
|
|
bootph-some-ram;
|
|
};
|
|
|
|
&{/soc@0/bus@44000000/i2c@44350000/pmic@25} {
|
|
bootph-pre-ram;
|
|
bootph-some-ram;
|
|
};
|
|
|
|
&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} {
|
|
bootph-pre-ram;
|
|
bootph-some-ram;
|
|
};
|
|
|
|
&pinctrl_lpi2c2 {
|
|
bootph-pre-ram;
|
|
bootph-some-ram;
|
|
};
|
|
|
|
&fec {
|
|
phy-reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
|
|
phy-reset-duration = <15>;
|
|
phy-reset-post-delay = <100>;
|
|
};
|
|
|
|
&eqos {
|
|
compatible = "fsl,imx-eqos";
|
|
};
|
|
|
|
ðphy1 {
|
|
reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
|
|
reset-assert-us = <15000>;
|
|
reset-deassert-us = <100000>;
|
|
};
|
|
|
|
&s4muap {
|
|
bootph-pre-ram;
|
|
bootph-some-ram;
|
|
status = "okay";
|
|
};
|
|
|
|
&clk {
|
|
bootph-all;
|
|
bootph-pre-ram;
|
|
/delete-property/ assigned-clocks;
|
|
/delete-property/ assigned-clock-rates;
|
|
/delete-property/ assigned-clock-parents;
|
|
};
|
|
|
|
&osc_32k {
|
|
bootph-all;
|
|
bootph-pre-ram;
|
|
};
|
|
|
|
&osc_24m {
|
|
bootph-all;
|
|
bootph-pre-ram;
|
|
};
|
|
|
|
&clk_ext1 {
|
|
bootph-all;
|
|
bootph-pre-ram;
|
|
};
|