mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-04 02:20:25 +00:00
9043adee3e
Commit 68dcbdd594 ("ARM: imx: Add weak default reset_cpu()") caused
the 'reset' command in U-Boot to not cause a board reset.
Fix it by switching to the watchdog driver model via sysreset, which
is the preferred method for implementing the watchdog reset.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
74 lines
1.6 KiB
Text
74 lines
1.6 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR MIT
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#include "imx7s-u-boot.dtsi"
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/ {
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdog1>;
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bootph-pre-ram;
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};
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};
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&fec2 {
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status = "disable";
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};
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&usbotg1 {
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dr_mode = "peripheral";
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};
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
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};
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&pinctrl_usdhc1 {
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fsl,pins = <
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MX7D_PAD_SD1_CMD__SD1_CMD 0x59
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MX7D_PAD_SD1_CLK__SD1_CLK 0x19
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MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
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MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
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MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
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MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
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>;
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};
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&iomuxc {
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pinctrl_usdhc1_gpio: usdhc1gpiogrp {
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fsl,pins = <
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MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
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MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
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MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
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MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */
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>;
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};
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pinctrl_usdhc1_100mhz: usdhc1100mhzgrp {
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fsl,pins = <
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MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
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MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
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MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
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MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
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MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
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MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
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>;
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};
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pinctrl_usdhc1_200mhz: usdhc1200mhzgrp {
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fsl,pins = <
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MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
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MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
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MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
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MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
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MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
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MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
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>;
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};
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};
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&wdog1 {
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bootph-pre-ram;
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};
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