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https://github.com/AsahiLinux/u-boot
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174d728471
Update my and DPs email address to match current setup. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
109 lines
2.5 KiB
C
109 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* (C) Copyright 2019 Xilinx, Inc.
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* Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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#define HALT 0
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#define RELEASE 1
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#define VERSAL_RPU_CFG_CPU_HALT_MASK 0x01
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#define VERSAL_RPU_GLBL_CTRL_SPLIT_LOCK_MASK 0x08
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#define VERSAL_RPU_GLBL_CTRL_TCM_COMB_MASK 0x40
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#define VERSAL_RPU_GLBL_CTRL_SLCLAMP_MASK 0x10
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#define VERSAL_CRLAPB_RST_LPD_AMBA_RST_MASK 0x04
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#define VERSAL_CRLAPB_RST_LPD_R50_RST_MASK 0x01
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#define VERSAL_CRLAPB_RST_LPD_R51_RST_MASK 0x02
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#define VERSAL_CRL_RST_CPU_R5_RESET_PGE_MASK 0x10
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#define VERSAL_CRLAPB_CPU_R5_CTRL_CLKACT_MASK 0x1000000
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static void set_r5_halt_mode(u8 halt, u8 mode)
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{
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u32 tmp;
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tmp = readl(&rpu_base->rpu0_cfg);
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if (halt == HALT)
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tmp &= ~VERSAL_RPU_CFG_CPU_HALT_MASK;
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else
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tmp |= VERSAL_RPU_CFG_CPU_HALT_MASK;
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writel(tmp, &rpu_base->rpu0_cfg);
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if (mode == TCM_LOCK) {
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tmp = readl(&rpu_base->rpu1_cfg);
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if (halt == HALT)
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tmp &= ~VERSAL_RPU_CFG_CPU_HALT_MASK;
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else
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tmp |= VERSAL_RPU_CFG_CPU_HALT_MASK;
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writel(tmp, &rpu_base->rpu1_cfg);
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}
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}
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static void set_r5_tcm_mode(u8 mode)
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{
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u32 tmp;
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tmp = readl(&rpu_base->rpu_glbl_ctrl);
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if (mode == TCM_LOCK) {
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tmp &= ~VERSAL_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
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tmp |= VERSAL_RPU_GLBL_CTRL_TCM_COMB_MASK |
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VERSAL_RPU_GLBL_CTRL_SLCLAMP_MASK;
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} else {
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tmp |= VERSAL_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
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tmp &= ~(VERSAL_RPU_GLBL_CTRL_TCM_COMB_MASK |
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VERSAL_RPU_GLBL_CTRL_SLCLAMP_MASK);
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}
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writel(tmp, &rpu_base->rpu_glbl_ctrl);
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}
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static void release_r5_reset(u8 mode)
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{
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u32 tmp;
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tmp = readl(&crlapb_base->rst_cpu_r5);
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tmp &= ~(VERSAL_CRLAPB_RST_LPD_AMBA_RST_MASK |
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VERSAL_CRLAPB_RST_LPD_R50_RST_MASK |
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VERSAL_CRL_RST_CPU_R5_RESET_PGE_MASK);
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if (mode == TCM_LOCK)
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tmp &= ~VERSAL_CRLAPB_RST_LPD_R51_RST_MASK;
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writel(tmp, &crlapb_base->rst_cpu_r5);
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}
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static void enable_clock_r5(void)
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{
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u32 tmp;
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tmp = readl(&crlapb_base->cpu_r5_ctrl);
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tmp |= VERSAL_CRLAPB_CPU_R5_CTRL_CLKACT_MASK;
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writel(tmp, &crlapb_base->cpu_r5_ctrl);
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}
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void initialize_tcm(bool mode)
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{
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if (!mode) {
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set_r5_tcm_mode(TCM_LOCK);
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set_r5_halt_mode(HALT, TCM_LOCK);
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enable_clock_r5();
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release_r5_reset(TCM_LOCK);
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} else {
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set_r5_tcm_mode(TCM_SPLIT);
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set_r5_halt_mode(HALT, TCM_SPLIT);
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enable_clock_r5();
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release_r5_reset(TCM_SPLIT);
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}
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}
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void tcm_init(u8 mode)
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{
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puts("WARNING: Initializing TCM overwrites TCM content\n");
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initialize_tcm(mode);
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memset((void *)VERSAL_TCM_BASE_ADDR, 0, VERSAL_TCM_SIZE);
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}
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