mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 17:07:38 +00:00
4e5114daf9
Synchronise device tree with linux v5.19-rc5. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
170 lines
4.3 KiB
Text
170 lines
4.3 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright 2021 Collabora Ltd.
|
|
* Copyright 2021 BSH Hausgeraete GmbH
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
#include "imx8mn-bsh-smm-s2-common.dtsi"
|
|
#include <dt-bindings/sound/tlv320aic31xx.h>
|
|
|
|
/ {
|
|
model = "BSH SMM S2 PRO";
|
|
compatible = "bsh,imx8mn-bsh-smm-s2pro", "fsl,imx8mn";
|
|
|
|
memory@40000000 {
|
|
device_type = "memory";
|
|
reg = <0x0 0x40000000 0x0 0x20000000>;
|
|
};
|
|
|
|
sound-tlv320aic31xx {
|
|
compatible = "fsl,imx-audio-tlv320aic31xx";
|
|
model = "tlv320aic31xx-hifi";
|
|
audio-cpu = <&sai3>;
|
|
audio-codec = <&tlv320dac3101>;
|
|
audio-asrc = <&easrc>;
|
|
audio-routing =
|
|
"Ext Spk", "SPL",
|
|
"Ext Spk", "SPR";
|
|
mclk-id = <PLL_CLKIN_BCLK>;
|
|
};
|
|
|
|
vdd_input: vdd_input {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "vdd_input";
|
|
regulator-min-microvolt = <5000000>;
|
|
regulator-max-microvolt = <5000000>;
|
|
};
|
|
};
|
|
|
|
&easrc {
|
|
fsl,asrc-rate = <48000>;
|
|
fsl,asrc-format = <10>;
|
|
status = "okay";
|
|
};
|
|
|
|
&i2c2 {
|
|
clock-frequency = <400000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c2>;
|
|
status = "okay";
|
|
|
|
tlv320dac3101: audio-codec@18 {
|
|
compatible = "ti,tlv320dac3101";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_dac_rst>;
|
|
reg = <0x18>;
|
|
#sound-dai-cells = <0>;
|
|
HPVDD-supply = <&buck4_reg>;
|
|
SPRVDD-supply = <&vdd_input>;
|
|
SPLVDD-supply = <&vdd_input>;
|
|
AVDD-supply = <&buck4_reg>;
|
|
IOVDD-supply = <&buck4_reg>;
|
|
DVDD-supply = <&buck5_reg>;
|
|
reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
|
|
ai31xx-micbias-vg = <MICBIAS_AVDDV>;
|
|
clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
|
|
};
|
|
};
|
|
|
|
&sai3 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_sai3>;
|
|
assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
|
|
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
|
|
assigned-clock-rates = <24576000>;
|
|
fsl,sai-mclk-direction-output;
|
|
status = "okay";
|
|
};
|
|
|
|
/* eMMC */
|
|
&usdhc1 {
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
|
pinctrl-0 = <&pinctrl_usdhc1>;
|
|
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
|
|
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
|
|
bus-width = <8>;
|
|
non-removable;
|
|
status = "okay";
|
|
};
|
|
|
|
&iomuxc {
|
|
pinctrl_dac_rst: dacrstgrp {
|
|
fsl,pins = <
|
|
MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 /* DAC_RST */
|
|
>;
|
|
};
|
|
|
|
pinctrl_espi2: espi2grp {
|
|
fsl,pins = <
|
|
MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x082
|
|
MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x082
|
|
MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x082
|
|
MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x040
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c2: i2c2grp {
|
|
fsl,pins = <
|
|
MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400000c3
|
|
MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400000c3
|
|
>;
|
|
};
|
|
|
|
pinctrl_sai3: sai3grp {
|
|
fsl,pins = <
|
|
MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
|
|
MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
|
|
MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1: usdhc1grp {
|
|
fsl,pins = <
|
|
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000090
|
|
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d0
|
|
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d0
|
|
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d0
|
|
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d0
|
|
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d0
|
|
MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d0
|
|
MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d0
|
|
MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d0
|
|
MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d0
|
|
MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x090
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
|
|
fsl,pins = <
|
|
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000094
|
|
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d4
|
|
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d4
|
|
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d4
|
|
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d4
|
|
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d4
|
|
MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d4
|
|
MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d4
|
|
MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d4
|
|
MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d4
|
|
MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x094
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
|
|
fsl,pins = <
|
|
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000096
|
|
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d6
|
|
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d6
|
|
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d6
|
|
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d6
|
|
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d6
|
|
MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d6
|
|
MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d6
|
|
MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d6
|
|
MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d6
|
|
MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x096
|
|
>;
|
|
};
|
|
};
|