u-boot/arch/arm/dts/imx6ulz-bsh-smm-m2.dts
Michael Trimarchi cc74cab86a bsh: imx6ulz_smm_m2: Add imx6ulz BSH SMM M2 boards
Introduce BSH SystemMaster (SMM) M2 board family, which consists of:
imx6ulz SMM M2 and imx6ulz SMM M2 PRO boards.

Add support for imx6ulz BSH SMM M2 board:

- 128 MiB DDR3 RAM
- 256MiB Nand
- USBOTG1 peripheral - fastboot.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-09-18 22:56:18 +02:00

146 lines
3.5 KiB
Text

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 BSH Hausgeraete GmbH
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "imx6ulz.dtsi"
/ {
model = "BSH SMM M2";
compatible = "bsh,imx6ulz-bsh-smm-m2", "fsl,imx6ull", "fsl,imx6ulz";
chosen {
stdout-path = &uart4;
};
usdhc2_pwrseq: usdhc2-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>;
};
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "brcm,bcm4330-bt";
max-speed = <3000000>;
shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
device-wakeup-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
};
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usbotg1 {
dr_mode = "peripheral";
srp-disable;
hnp-disable;
adp-disable;
status = "okay";
};
&usbphy1 {
fsl,tx-d-cal = <106>;
};
&usdhc2 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wlan>;
bus-width = <4>;
no-1-8-v;
non-removable;
cap-power-off-card;
keep-power-in-suspend;
cap-sdio-irq;
mmc-pwrseq = <&usdhc2_pwrseq>;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&gpio1>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
};
};
&wdog1 {
status = "okay";
};
&iomuxc {
pinctrl_gpmi_nand: gpmi-nand {
fsl,pins = <
MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b099
MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b099
MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x79 /* BT_REG_ON */
MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x100b1 /* BT_DEV_WAKE out */
MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0 /* BT_HOST_WAKE in */
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
>;
};
pinctrl_wlan: wlangrp {
fsl,pins = <
MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059
MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10059
MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059
MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x79 /* WL_REG_ON */
MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x100b1 /* WL_DEV_WAKE - WiFi_GPIO_4 - WiFi FW UART */
MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b1 /* WL_HOST_WAKE - WIFI_GPIO_0 - OOB IRQ */
MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT 0x4001b031 /* OSC 32Khz wifi clk in */
>;
};
};