mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
5ed8239383
The kernel DT of the SinA33 has evolved quite a bit. Make sure we sync it and its upstream DTSI to be able to use the OTG. The DTs were taken from the 4.13 kernel release. Reviewed-by: Łukasz Majewski <lukma@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
490 lines
11 KiB
Text
490 lines
11 KiB
Text
/*
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* Copyright 2014 Chen-Yu Tsai
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*
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* Chen-Yu Tsai <wens@csie.org>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "sun8i-a23-a33.dtsi"
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#include <dt-bindings/thermal/thermal.h>
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/ {
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cpu0_opp_table: opp_table0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-120000000 {
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opp-hz = /bits/ 64 <120000000>;
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opp-microvolt = <1040000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp-240000000 {
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opp-hz = /bits/ 64 <240000000>;
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opp-microvolt = <1040000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp-312000000 {
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opp-hz = /bits/ 64 <312000000>;
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opp-microvolt = <1040000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp-408000000 {
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <1040000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp-480000000 {
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opp-hz = /bits/ 64 <480000000>;
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opp-microvolt = <1040000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp-504000000 {
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opp-hz = /bits/ 64 <504000000>;
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opp-microvolt = <1040000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <1040000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp-648000000 {
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opp-hz = /bits/ 64 <648000000>;
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opp-microvolt = <1040000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp-720000000 {
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opp-hz = /bits/ 64 <720000000>;
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opp-microvolt = <1100000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp-816000000 {
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opp-hz = /bits/ 64 <816000000>;
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opp-microvolt = <1100000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp-912000000 {
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opp-hz = /bits/ 64 <912000000>;
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opp-microvolt = <1200000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp-1008000000 {
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opp-hz = /bits/ 64 <1008000000>;
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opp-microvolt = <1200000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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};
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cpus {
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cpu@0 {
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clocks = <&ccu CLK_CPUX>;
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clock-names = "cpu";
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operating-points-v2 = <&cpu0_opp_table>;
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#cooling-cells = <2>;
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};
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cpu@1 {
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operating-points-v2 = <&cpu0_opp_table>;
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};
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cpu@2 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <2>;
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operating-points-v2 = <&cpu0_opp_table>;
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};
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cpu@3 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <3>;
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operating-points-v2 = <&cpu0_opp_table>;
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};
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};
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de: display-engine {
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compatible = "allwinner,sun8i-a33-display-engine";
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allwinner,pipelines = <&fe0>;
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status = "disabled";
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};
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iio-hwmon {
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compatible = "iio-hwmon";
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io-channels = <&ths>;
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};
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mali_opp_table: gpu-opp-table {
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compatible = "operating-points-v2";
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opp-144000000 {
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opp-hz = /bits/ 64 <144000000>;
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};
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opp-240000000 {
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opp-hz = /bits/ 64 <240000000>;
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};
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opp-384000000 {
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opp-hz = /bits/ 64 <384000000>;
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};
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};
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memory {
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reg = <0x40000000 0x80000000>;
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};
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sound: sound {
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compatible = "simple-audio-card";
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simple-audio-card,name = "sun8i-a33-audio";
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simple-audio-card,format = "i2s";
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simple-audio-card,frame-master = <&link_codec>;
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simple-audio-card,bitclock-master = <&link_codec>;
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simple-audio-card,mclk-fs = <512>;
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simple-audio-card,aux-devs = <&codec_analog>;
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simple-audio-card,routing =
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"Left DAC", "AIF1 Slot 0 Left",
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"Right DAC", "AIF1 Slot 0 Right";
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status = "disabled";
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simple-audio-card,cpu {
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sound-dai = <&dai>;
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};
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link_codec: simple-audio-card,codec {
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sound-dai = <&codec>;
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};
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};
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soc@01c00000 {
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tcon0: lcd-controller@01c0c000 {
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compatible = "allwinner,sun8i-a33-tcon";
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reg = <0x01c0c000 0x1000>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_LCD>,
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<&ccu CLK_LCD_CH0>;
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clock-names = "ahb",
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"tcon-ch0";
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clock-output-names = "tcon-pixel-clock";
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resets = <&ccu RST_BUS_LCD>;
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reset-names = "lcd";
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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tcon0_in: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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tcon0_in_drc0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&drc0_out_tcon0>;
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};
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};
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tcon0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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};
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};
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crypto: crypto-engine@01c15000 {
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compatible = "allwinner,sun4i-a10-crypto";
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reg = <0x01c15000 0x1000>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
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clock-names = "ahb", "mod";
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resets = <&ccu RST_BUS_SS>;
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reset-names = "ahb";
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};
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dai: dai@01c22c00 {
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#sound-dai-cells = <0>;
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compatible = "allwinner,sun6i-a31-i2s";
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reg = <0x01c22c00 0x200>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
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clock-names = "apb", "mod";
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resets = <&ccu RST_BUS_CODEC>;
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dmas = <&dma 15>, <&dma 15>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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codec: codec@01c22e00 {
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#sound-dai-cells = <0>;
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compatible = "allwinner,sun8i-a33-codec";
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reg = <0x01c22e00 0x400>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
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clock-names = "bus", "mod";
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status = "disabled";
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};
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ths: ths@01c25000 {
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compatible = "allwinner,sun8i-a33-ths";
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reg = <0x01c25000 0x100>;
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#thermal-sensor-cells = <0>;
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#io-channel-cells = <0>;
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};
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fe0: display-frontend@01e00000 {
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compatible = "allwinner,sun8i-a33-display-frontend";
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reg = <0x01e00000 0x20000>;
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
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<&ccu CLK_DRAM_DE_FE>;
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clock-names = "ahb", "mod",
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"ram";
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resets = <&ccu RST_BUS_DE_FE>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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fe0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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fe0_out_be0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&be0_in_fe0>;
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};
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};
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};
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};
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be0: display-backend@01e60000 {
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compatible = "allwinner,sun8i-a33-display-backend";
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reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
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reg-names = "be", "sat";
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
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<&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
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clock-names = "ahb", "mod",
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"ram", "sat";
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resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
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reset-names = "be", "sat";
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assigned-clocks = <&ccu CLK_DE_BE>;
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assigned-clock-rates = <300000000>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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be0_in: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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be0_in_fe0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&fe0_out_be0>;
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};
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};
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be0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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be0_out_drc0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&drc0_in_be0>;
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};
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};
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};
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};
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drc0: drc@01e70000 {
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compatible = "allwinner,sun8i-a33-drc";
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reg = <0x01e70000 0x10000>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
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<&ccu CLK_DRAM_DRC>;
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clock-names = "ahb", "mod", "ram";
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resets = <&ccu RST_BUS_DRC>;
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assigned-clocks = <&ccu CLK_DRC>;
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assigned-clock-rates = <300000000>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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drc0_in: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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drc0_in_be0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&be0_out_drc0>;
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};
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};
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drc0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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drc0_out_tcon0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&tcon0_in_drc0>;
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};
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};
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};
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};
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};
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thermal-zones {
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cpu_thermal {
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/* milliseconds */
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&ths>;
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cooling-maps {
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map0 {
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trip = <&cpu_alert0>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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map1 {
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trip = <&cpu_alert1>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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map2 {
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trip = <&gpu_alert0>;
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cooling-device = <&mali 1 THERMAL_NO_LIMIT>;
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};
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map3 {
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trip = <&gpu_alert1>;
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cooling-device = <&mali 2 THERMAL_NO_LIMIT>;
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};
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};
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trips {
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cpu_alert0: cpu_alert0 {
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/* milliCelsius */
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temperature = <75000>;
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hysteresis = <2000>;
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type = "passive";
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};
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gpu_alert0: gpu_alert0 {
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/* milliCelsius */
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_alert1: cpu_alert1 {
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/* milliCelsius */
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temperature = <90000>;
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hysteresis = <2000>;
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type = "hot";
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};
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gpu_alert1: gpu_alert1 {
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/* milliCelsius */
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temperature = <95000>;
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hysteresis = <2000>;
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type = "hot";
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};
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cpu_crit: cpu_crit {
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/* milliCelsius */
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temperature = <110000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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};
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};
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&ccu {
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compatible = "allwinner,sun8i-a33-ccu";
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};
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&mali {
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operating-points-v2 = <&mali_opp_table>;
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};
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&pio {
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compatible = "allwinner,sun8i-a33-pinctrl";
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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uart0_pins_b: uart0@1 {
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pins = "PB0", "PB1";
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function = "uart0";
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};
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};
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&usb_otg {
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compatible = "allwinner,sun8i-a33-musb";
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};
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&usbphy {
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compatible = "allwinner,sun8i-a33-usb-phy";
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reg = <0x01c19400 0x14>, <0x01c1a800 0x4>;
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reg-names = "phy_ctrl", "pmu1";
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};
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