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https://github.com/AsahiLinux/u-boot
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7a540eeecc
As part of disabling caches MMU as well gets disabled. But MMU is not available on all armv7 cores like R5F. So disable MMU only if it is available. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
317 lines
7 KiB
C
317 lines
7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*/
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#include <common.h>
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#include <asm/system.h>
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#include <asm/cache.h>
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#include <linux/compiler.h>
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#include <asm/armv7_mpu.h>
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#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_SYS_ARM_MMU
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__weak void arm_init_before_mmu(void)
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{
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}
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__weak void arm_init_domains(void)
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{
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}
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void set_section_dcache(int section, enum dcache_option option)
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{
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#ifdef CONFIG_ARMV7_LPAE
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u64 *page_table = (u64 *)gd->arch.tlb_addr;
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/* Need to set the access flag to not fault */
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u64 value = TTB_SECT_AP | TTB_SECT_AF;
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#else
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u32 *page_table = (u32 *)gd->arch.tlb_addr;
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u32 value = TTB_SECT_AP;
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#endif
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/* Add the page offset */
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value |= ((u32)section << MMU_SECTION_SHIFT);
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/* Add caching bits */
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value |= option;
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/* Set PTE */
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page_table[section] = value;
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}
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__weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
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{
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debug("%s: Warning: not implemented\n", __func__);
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}
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void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
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enum dcache_option option)
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{
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#ifdef CONFIG_ARMV7_LPAE
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u64 *page_table = (u64 *)gd->arch.tlb_addr;
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#else
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u32 *page_table = (u32 *)gd->arch.tlb_addr;
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#endif
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unsigned long startpt, stoppt;
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unsigned long upto, end;
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end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
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start = start >> MMU_SECTION_SHIFT;
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#ifdef CONFIG_ARMV7_LPAE
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debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size,
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option);
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#else
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debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
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option);
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#endif
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for (upto = start; upto < end; upto++)
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set_section_dcache(upto, option);
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/*
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* Make sure range is cache line aligned
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* Only CPU maintains page tables, hence it is safe to always
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* flush complete cache lines...
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*/
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startpt = (unsigned long)&page_table[start];
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startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
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stoppt = (unsigned long)&page_table[end];
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stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE);
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mmu_page_table_flush(startpt, stoppt);
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}
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__weak void dram_bank_mmu_setup(int bank)
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{
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bd_t *bd = gd->bd;
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int i;
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debug("%s: bank: %d\n", __func__, bank);
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for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
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i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
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(bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
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i++) {
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#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
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set_section_dcache(i, DCACHE_WRITETHROUGH);
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#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
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set_section_dcache(i, DCACHE_WRITEALLOC);
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#else
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set_section_dcache(i, DCACHE_WRITEBACK);
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#endif
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}
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}
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/* to activate the MMU we need to set up virtual memory: use 1M areas */
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static inline void mmu_setup(void)
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{
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int i;
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u32 reg;
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arm_init_before_mmu();
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/* Set up an identity-mapping for all 4GB, rw for everyone */
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for (i = 0; i < ((4096ULL * 1024 * 1024) >> MMU_SECTION_SHIFT); i++)
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set_section_dcache(i, DCACHE_OFF);
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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dram_bank_mmu_setup(i);
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}
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#if defined(CONFIG_ARMV7_LPAE) && __LINUX_ARM_ARCH__ != 4
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/* Set up 4 PTE entries pointing to our 4 1GB page tables */
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for (i = 0; i < 4; i++) {
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u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4));
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u64 tpt = gd->arch.tlb_addr + (4096 * i);
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page_table[i] = tpt | TTB_PAGETABLE;
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}
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reg = TTBCR_EAE;
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#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
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reg |= TTBCR_ORGN0_WT | TTBCR_IRGN0_WT;
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#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
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reg |= TTBCR_ORGN0_WBWA | TTBCR_IRGN0_WBWA;
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#else
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reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA;
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#endif
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if (is_hyp()) {
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/* Set HTCR to enable LPAE */
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asm volatile("mcr p15, 4, %0, c2, c0, 2"
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: : "r" (reg) : "memory");
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/* Set HTTBR0 */
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asm volatile("mcrr p15, 4, %0, %1, c2"
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:
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: "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
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: "memory");
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/* Set HMAIR */
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asm volatile("mcr p15, 4, %0, c10, c2, 0"
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: : "r" (MEMORY_ATTRIBUTES) : "memory");
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} else {
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/* Set TTBCR to enable LPAE */
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asm volatile("mcr p15, 0, %0, c2, c0, 2"
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: : "r" (reg) : "memory");
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/* Set 64-bit TTBR0 */
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asm volatile("mcrr p15, 0, %0, %1, c2"
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:
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: "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
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: "memory");
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/* Set MAIR */
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asm volatile("mcr p15, 0, %0, c10, c2, 0"
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: : "r" (MEMORY_ATTRIBUTES) : "memory");
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}
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#elif defined(CONFIG_CPU_V7A)
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if (is_hyp()) {
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/* Set HTCR to disable LPAE */
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asm volatile("mcr p15, 4, %0, c2, c0, 2"
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: : "r" (0) : "memory");
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} else {
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/* Set TTBCR to disable LPAE */
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asm volatile("mcr p15, 0, %0, c2, c0, 2"
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: : "r" (0) : "memory");
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}
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/* Set TTBR0 */
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reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
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#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
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reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT;
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#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
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reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA;
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#else
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reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB;
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#endif
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asm volatile("mcr p15, 0, %0, c2, c0, 0"
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: : "r" (reg) : "memory");
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#else
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/* Copy the page table address to cp15 */
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asm volatile("mcr p15, 0, %0, c2, c0, 0"
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: : "r" (gd->arch.tlb_addr) : "memory");
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#endif
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/* Set the access control to all-supervisor */
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asm volatile("mcr p15, 0, %0, c3, c0, 0"
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: : "r" (~0));
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arm_init_domains();
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/* and enable the mmu */
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reg = get_cr(); /* get control reg. */
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set_cr(reg | CR_M);
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}
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static int mmu_enabled(void)
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{
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return get_cr() & CR_M;
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}
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#endif /* CONFIG_SYS_ARM_MMU */
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/* cache_bit must be either CR_I or CR_C */
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static void cache_enable(uint32_t cache_bit)
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{
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uint32_t reg;
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/* The data cache is not active unless the mmu/mpu is enabled too */
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#ifdef CONFIG_SYS_ARM_MMU
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if ((cache_bit == CR_C) && !mmu_enabled())
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mmu_setup();
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#elif defined(CONFIG_SYS_ARM_MPU)
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if ((cache_bit == CR_C) && !mpu_enabled()) {
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printf("Consider enabling MPU before enabling caches\n");
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return;
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}
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#endif
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reg = get_cr(); /* get control reg. */
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set_cr(reg | cache_bit);
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}
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/* cache_bit must be either CR_I or CR_C */
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static void cache_disable(uint32_t cache_bit)
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{
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uint32_t reg;
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reg = get_cr();
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if (cache_bit == CR_C) {
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/* if cache isn;t enabled no need to disable */
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if ((reg & CR_C) != CR_C)
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return;
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#ifdef CONFIG_SYS_ARM_MMU
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/* if disabling data cache, disable mmu too */
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cache_bit |= CR_M;
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#endif
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}
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reg = get_cr();
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#ifdef CONFIG_SYS_ARM_MMU
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if (cache_bit == (CR_C | CR_M))
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#elif defined(CONFIG_SYS_ARM_MPU)
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if (cache_bit == CR_C)
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#endif
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flush_dcache_all();
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set_cr(reg & ~cache_bit);
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}
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#endif
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#if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
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void icache_enable (void)
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{
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return;
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}
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void icache_disable (void)
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{
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return;
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}
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int icache_status (void)
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{
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return 0; /* always off */
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}
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#else
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void icache_enable(void)
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{
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cache_enable(CR_I);
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}
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void icache_disable(void)
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{
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cache_disable(CR_I);
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}
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int icache_status(void)
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{
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return (get_cr() & CR_I) != 0;
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}
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#endif
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#if CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
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void dcache_enable (void)
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{
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return;
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}
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void dcache_disable (void)
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{
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return;
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}
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int dcache_status (void)
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{
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return 0; /* always off */
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}
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#else
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void dcache_enable(void)
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{
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cache_enable(CR_C);
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}
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void dcache_disable(void)
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{
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cache_disable(CR_C);
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}
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int dcache_status(void)
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{
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return (get_cr() & CR_C) != 0;
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}
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#endif
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