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Stefan Roese 28e94bb2f7 ppc4xx/POST: Handle cached SDRAM correctly in Denali (440EPx) ECC POST 
This patch fixes a problem in the Denali (440EPx) SDRAM ECC POST test.
When cache is enabled in the SDRAM area, the values written to SDRAM
need to be flushed from cache to SDRAM using the dcfb instruction.

Without this patch the POST ECC test failed. Now its working again on
platforms with cache enabled in SDRAM.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-11-28 11:06:47 +01:00
..
board Switch from archive libraries to partial linking 2010-11-17 21:02:18 +01:00
cpu ppc4xx/POST: Handle cached SDRAM correctly in Denali (440EPx) ECC POST 2010-11-28 11:06:47 +01:00
drivers Merge branch 'master' of git://git.denx.de/u-boot-i2c 2010-11-19 22:02:40 +01:00
lib_powerpc Switch from archive libraries to partial linking 2010-11-17 21:02:18 +01:00
Makefile Switch from archive libraries to partial linking 2010-11-17 21:02:18 +01:00
post.c Replace CONFIG_RELOC_FIXUP_WORKS by CONFIG_NEEDS_MANUAL_RELOC 2010-10-29 21:32:07 +02:00
rules.mk Switch from archive libraries to partial linking 2010-11-17 21:02:18 +01:00
tests.c ppc4xx/POST: Add board specific UART POST test to lwmon5 2010-10-20 10:08:08 +02:00