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b2d527a8b9
LWMON5 DSPIC POST uses the watch-dog scratch register. So, make the CFG_DSPIC_TEST_ADDR definition more readable. Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
615 lines
24 KiB
C
615 lines
24 KiB
C
/*
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* (C) Copyright 2007-2008
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/************************************************************************
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* lwmon5.h - configuration for lwmon5 board
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***********************************************************************/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*-----------------------------------------------------------------------
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* High Level Configuration Options
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*----------------------------------------------------------------------*/
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#define CONFIG_LWMON5 1 /* Board is lwmon5 */
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#define CONFIG_440EPX 1 /* Specific PPC440EPx */
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#define CONFIG_440 1 /* ... PPC440 family */
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */
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#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
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#define CONFIG_BOARD_RESET 1 /* Call board_reset */
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*----------------------------------------------------------------------*/
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#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
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#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */
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#define CFG_BOOT_BASE_ADDR 0xf0000000
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#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
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#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH */
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_LIME_BASE_0 0xc0000000
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#define CFG_LIME_BASE_1 0xc1000000
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#define CFG_LIME_BASE_2 0xc2000000
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#define CFG_LIME_BASE_3 0xc3000000
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#define CFG_FPGA_BASE_0 0xc4000000
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#define CFG_FPGA_BASE_1 0xc4200000
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#define CFG_OCM_BASE 0xe0010000 /* ocm */
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#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
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#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
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#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
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#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
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#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
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/* Don't change either of these */
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#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
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#define CFG_USB2D0_BASE 0xe0000100
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#define CFG_USB_DEVICE 0xe0000000
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#define CFG_USB_HOST 0xe0000400
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/*-----------------------------------------------------------------------
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* Initial RAM & stack pointer
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*----------------------------------------------------------------------*/
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/*
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* On LWMON5 we use D-cache as init-ram and stack pointer. We also move
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* the POST_WORD from OCM to a 440EPx register that preserves it's
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* content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
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* for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
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*/
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#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
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#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
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#define CFG_INIT_RAM_END (4 << 10)
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#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6)
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/* unused GPT0 COMP reg */
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#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
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/* 440EPx errata CHIP 11 */
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/* Additional registers for watchdog timer post test */
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#define CFG_WATCHDOG_TIME_ADDR (CFG_PERIPHERAL_BASE + GPT0_MASK2)
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#define CFG_WATCHDOG_FLAGS_ADDR (CFG_PERIPHERAL_BASE + GPT0_MASK1)
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#define CFG_DSPIC_TEST_ADDR CFG_WATCHDOG_FLAGS_ADDR
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#define CFG_WATCHDOG_MAGIC 0x12480000
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#define CFG_WATCHDOG_MAGIC_MASK 0xFFFF0000
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#define CFG_DSPIC_TEST_MASK 0x00000001
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/*-----------------------------------------------------------------------
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* Serial Port
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*----------------------------------------------------------------------*/
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#undef CFG_EXT_SERIAL_CLOCK /* no external clock provided */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SERIAL_MULTI 1
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/* define this if you want console on UART1 */
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#define CONFIG_UART1_CONSOLE 1 /* use UART1 as console */
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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/*-----------------------------------------------------------------------
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* Environment
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*----------------------------------------------------------------------*/
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#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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/*-----------------------------------------------------------------------
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* FLASH related
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*----------------------------------------------------------------------*/
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#define CFG_FLASH_CFI /* The flash is CFI compatible */
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#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CFG_FLASH0 0xFC000000
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#define CFG_FLASH1 0xF8000000
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#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 }
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#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
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#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
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#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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/*-----------------------------------------------------------------------
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* DDR SDRAM
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*----------------------------------------------------------------------*/
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#define CFG_MBYTES_SDRAM (256) /* 256MB */
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#define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
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#define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */
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#define CONFIG_DDR_ECC 1 /* enable ECC */
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#define CFG_POST_ECC_ON CFG_POST_ECC
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/* POST support */
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#define CONFIG_POST (CFG_POST_CACHE | \
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CFG_POST_CPU | \
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CFG_POST_ECC_ON | \
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CFG_POST_ETHER | \
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CFG_POST_FPU | \
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CFG_POST_I2C | \
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CFG_POST_MEMORY | \
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CFG_POST_RTC | \
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CFG_POST_SPR | \
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CFG_POST_UART | \
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CFG_POST_SYSMON | \
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CFG_POST_WATCHDOG | \
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CFG_POST_DSP | \
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CFG_POST_BSPEC1 | \
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CFG_POST_BSPEC2 | \
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CFG_POST_BSPEC3 | \
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CFG_POST_BSPEC4 | \
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CFG_POST_BSPEC5)
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#define CONFIG_POST_WATCHDOG {\
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"Watchdog timer test", \
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"watchdog", \
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"This test checks the watchdog timer.", \
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POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \
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&lwmon5_watchdog_post_test, \
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NULL, \
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NULL, \
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CFG_POST_WATCHDOG \
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}
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#define CONFIG_POST_BSPEC1 {\
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"dsPIC init test", \
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"dspic_init", \
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"This test returns result of dsPIC READY test run earlier.", \
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POST_RAM | POST_ALWAYS, \
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&dspic_init_post_test, \
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NULL, \
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NULL, \
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CFG_POST_BSPEC1 \
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}
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#define CONFIG_POST_BSPEC2 {\
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"dsPIC test", \
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"dspic", \
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"This test gets result of dsPIC POST and dsPIC version.", \
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POST_RAM | POST_ALWAYS, \
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&dspic_post_test, \
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NULL, \
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NULL, \
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CFG_POST_BSPEC2 \
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}
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#define CONFIG_POST_BSPEC3 {\
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"FPGA test", \
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"fpga", \
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"This test checks FPGA registers and memory.", \
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POST_RAM | POST_ALWAYS, \
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&fpga_post_test, \
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NULL, \
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NULL, \
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CFG_POST_BSPEC3 \
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}
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#define CONFIG_POST_BSPEC4 {\
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"GDC test", \
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"gdc", \
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"This test checks GDC registers and memory.", \
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POST_RAM | POST_ALWAYS, \
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&gdc_post_test, \
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NULL, \
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NULL, \
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CFG_POST_BSPEC4 \
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}
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#define CONFIG_POST_BSPEC5 {\
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"SYSMON1 test", \
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"sysmon1", \
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"This test checks GPIO_62_EPX pin indicating power failure.", \
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POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \
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&sysmon1_post_test, \
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NULL, \
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NULL, \
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CFG_POST_BSPEC5 \
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}
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#define CFG_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
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#define CONFIG_LOGBUFFER
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/* Reserve GPT0_COMP1-COMP5 for logbuffer header */
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#define CONFIG_ALT_LH_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP1)
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#define CONFIG_ALT_LB_ADDR (CFG_OCM_BASE)
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#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
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/*-----------------------------------------------------------------------
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* I2C
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*----------------------------------------------------------------------*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_EEPROM_ADDR 0x53 /* EEPROM AT24C128 */
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#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
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#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */
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/* 64 byte page write mode using*/
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/* last 6 bits of the address */
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
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#define CFG_EEPROM_PAGE_WRITE_ENABLE
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#define CONFIG_RTC_PCF8563 1 /* enable Philips PCF8563 RTC */
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#define CFG_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
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#define CFG_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
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#define CFG_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */
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#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
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#if 0
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#define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */
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#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n"
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#define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */
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#endif
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#define CONFIG_PREBOOT "setenv bootdelay 15"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"hostname=lwmon5\0" \
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"netdev=eth0\0" \
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"unlock=yes\0" \
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"logversion=2\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
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"addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
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"flash_nfs=run nfsargs addip addtty addmisc;" \
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"bootm ${kernel_addr}\0" \
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"flash_self=run ramargs addip addtty addmisc;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};" \
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"run nfsargs addip addtty addmisc;bootm\0" \
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"rootpath=/opt/eldk/ppc_4xxFP\0" \
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"bootfile=/tftpboot/lwmon5/uImage\0" \
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"kernel_addr=FC000000\0" \
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"ramdisk_addr=FC180000\0" \
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"load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
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"update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \
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"cp.b 200000 FFF80000 80000\0" \
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"upd=run load update\0" \
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"lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \
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"autoscr 200000\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_self"
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#endif
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_IBM_EMAC4_V4 1
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */
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#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
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#define CONFIG_PHY_RESET_DELAY 300
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#define CONFIG_HAS_ETH0
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#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
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#define CONFIG_NET_MULTI 1
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#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
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#define CONFIG_PHY1_ADDR 1
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/* Video console */
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#define CONFIG_VIDEO
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#define CONFIG_VIDEO_MB862xx
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_CONSOLE_EXTRA_INFO
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#define VIDEO_FB_16BPP_PIXEL_SWAP
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#define CONFIG_VGA_AS_SINGLE_DEVICE
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#define CONFIG_VIDEO_SW_CURSOR
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#define CONFIG_SPLASH_SCREEN
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/* USB */
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#ifdef CONFIG_440EPX
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#define CONFIG_USB_OHCI
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#define CONFIG_USB_STORAGE
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/* Comment this out to enable USB 1.1 device */
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#define USB_2_0_DEVICE
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#endif /* CONFIG_440EPX */
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/* Partitions */
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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#define CONFIG_ISO_PARTITION
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DIAG
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_LOG
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_SDRAM
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#ifdef CONFIG_VIDEO
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#define CONFIG_CMD_BMP
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#endif
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#ifdef CONFIG_440EPX
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#define CONFIG_CMD_USB
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#endif
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/*-----------------------------------------------------------------------
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* Miscellaneous configurable options
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*----------------------------------------------------------------------*/
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#define CONFIG_SUPPORT_VFAT
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
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#ifdef CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#endif
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_LOOPW 1 /* enable loopw command */
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#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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/*-----------------------------------------------------------------------
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* PCI stuff
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*----------------------------------------------------------------------*/
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/* General PCI */
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#define CONFIG_PCI /* include pci support */
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#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
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/* Board-specific PCI */
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#define CFG_PCI_TARGET_INIT
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#define CFG_PCI_MASTER_INIT
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#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
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#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
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#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
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#define CONFIG_WD_PERIOD 40000 /* in usec */
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#define CONFIG_WD_MAX_RATE 66600 /* in ticks */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* External Bus Controller (EBC) Setup
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*----------------------------------------------------------------------*/
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#define CFG_FLASH CFG_FLASH_BASE
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/* Memory Bank 0 (NOR-FLASH) initialization */
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#define CFG_EBC_PB0AP 0x03050200
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#define CFG_EBC_PB0CR (CFG_FLASH | 0xfc000)
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/* Memory Bank 1 (Lime) initialization */
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#define CFG_EBC_PB1AP 0x01004380
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#define CFG_EBC_PB1CR (CFG_LIME_BASE_0 | 0xdc000)
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/* Memory Bank 2 (FPGA) initialization */
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#define CFG_EBC_PB2AP 0x01004400
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#define CFG_EBC_PB2CR (CFG_FPGA_BASE_0 | 0x1c000)
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/* Memory Bank 3 (FPGA2) initialization */
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#define CFG_EBC_PB3AP 0x01004400
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#define CFG_EBC_PB3CR (CFG_FPGA_BASE_1 | 0x1c000)
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#define CFG_EBC_CFG 0xb8400000
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/*-----------------------------------------------------------------------
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* Graphics (Fujitsu Lime)
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*----------------------------------------------------------------------*/
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/* SDRAM Clock frequency adjustment register */
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#define CFG_LIME_SDRAM_CLOCK 0xC1FC0038
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/* Lime Clock frequency is to set 100MHz */
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#define CFG_LIME_CLOCK_100MHZ 0x00000
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#if 0
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/* Lime Clock frequency for 133MHz */
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#define CFG_LIME_CLOCK_133MHZ 0x10000
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#endif
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/* SDRAM Parameter register */
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#define CFG_LIME_MMR 0xC1FCFFFC
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/* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
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and pixel flare on display when 133MHz was configured. According to
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SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */
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#ifdef CFG_LIME_CLOCK_133MHZ
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#define CFG_LIME_MMR_VALUE 0x414FB7F3
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#else
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#define CFG_LIME_MMR_VALUE 0x414FB7F2
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#endif
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/*-----------------------------------------------------------------------
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* GPIO Setup
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*----------------------------------------------------------------------*/
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#define CFG_GPIO_PHY1_RST 12
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#define CFG_GPIO_FLASH_WP 14
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#define CFG_GPIO_PHY0_RST 22
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#define CFG_GPIO_DSPIC_READY 51
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#define CFG_GPIO_EEPROM_EXT_WP 55
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#define CFG_GPIO_HIGHSIDE 56
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#define CFG_GPIO_EEPROM_INT_WP 57
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#define CFG_GPIO_BOARD_RESET 58
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#define CFG_GPIO_LIME_S 59
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#define CFG_GPIO_LIME_RST 60
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#define CFG_GPIO_SYSMON_STATUS 62
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#define CFG_GPIO_WATCHDOG 63
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/*-----------------------------------------------------------------------
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* PPC440 GPIO Configuration
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*/
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#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
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{ \
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/* GPIO Core 0 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
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}, \
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{ \
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/* GPIO Core 1 */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
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{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
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{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
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|
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
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|
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
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|
} \
|
|
}
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|
|
|
/*
|
|
* Internal Definitions
|
|
*
|
|
* Boot Flags
|
|
*/
|
|
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
|
#define BOOTFLAG_WARM 0x02 /* Software reboot */
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|
|
|
#if defined(CONFIG_CMD_KGDB)
|
|
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
|
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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|
#endif
|
|
#endif /* __CONFIG_H */
|