mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 02:51:00 +00:00
ee91d46557
With Device Manager firmware in an elf file form, we cannot load the FIT image to the exact same address as any of the executable sections of the elf file itself is located. However, the device tree descriptions for the ARMV8 bootloader/OS includes DDR regions only the final sections in DDR where the Device Manager firmware is actually executing out of. As the R5 uC is usually operating at a slower rate than an ARMv8 MPU, by starting the Armv8 ahead of parsing the elf and copying the correct sections to the required memories creates a race condition where the ARMv8 could overwrite the elf image loaded from the FIT image prior to the R5 completing parsing and putting the correct sections of elf in the required memory locations. OR create rather obscure debug conditions where data in the section is being modified by ARMV8 OS while the elf copy is in progress. To prevent all these conditions, lets make sure that the elf parse and copy operations are completed ahead of ARMv8 being released to execute. We will pay a penalty of elf copy time, but that is a valid tradeoff in comparison to debug of alternate scenarios. Signed-off-by: Nishanth Menon <nm@ti.com>
551 lines
13 KiB
C
551 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* K3: Common Architecture initialization
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*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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* Lokesh Vutla <lokeshvutla@ti.com>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <image.h>
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#include <init.h>
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#include <log.h>
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#include <spl.h>
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#include <asm/global_data.h>
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#include "common.h"
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#include <dm.h>
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#include <remoteproc.h>
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#include <asm/cache.h>
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#include <linux/soc/ti/ti_sci_protocol.h>
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#include <fdt_support.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <fs_loader.h>
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#include <fs.h>
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#include <env.h>
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#include <elf.h>
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#include <soc.h>
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#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)
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enum {
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IMAGE_ID_ATF,
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IMAGE_ID_OPTEE,
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IMAGE_ID_SPL,
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IMAGE_ID_DM_FW,
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IMAGE_AMT,
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};
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#if CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS)
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static const char *image_os_match[IMAGE_AMT] = {
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"arm-trusted-firmware",
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"tee",
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"U-Boot",
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"DM",
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};
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#endif
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static struct image_info fit_image_info[IMAGE_AMT];
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#endif
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struct ti_sci_handle *get_ti_sci_handle(void)
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{
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struct udevice *dev;
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int ret;
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ret = uclass_get_device_by_driver(UCLASS_FIRMWARE,
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DM_DRIVER_GET(ti_sci), &dev);
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if (ret)
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panic("Failed to get SYSFW (%d)\n", ret);
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return (struct ti_sci_handle *)ti_sci_get_handle_from_sysfw(dev);
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}
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void k3_sysfw_print_ver(void)
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{
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struct ti_sci_handle *ti_sci = get_ti_sci_handle();
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char fw_desc[sizeof(ti_sci->version.firmware_description) + 1];
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/*
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* Output System Firmware version info. Note that since the
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* 'firmware_description' field is not guaranteed to be zero-
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* terminated we manually add a \0 terminator if needed. Further
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* note that we intentionally no longer rely on the extended
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* printf() formatter '%.*s' to not having to require a more
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* full-featured printf() implementation.
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*/
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strncpy(fw_desc, ti_sci->version.firmware_description,
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sizeof(ti_sci->version.firmware_description));
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fw_desc[sizeof(fw_desc) - 1] = '\0';
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printf("SYSFW ABI: %d.%d (firmware rev 0x%04x '%s')\n",
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ti_sci->version.abi_major, ti_sci->version.abi_minor,
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ti_sci->version.firmware_revision, fw_desc);
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}
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void mmr_unlock(phys_addr_t base, u32 partition)
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{
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/* Translate the base address */
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phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
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/* Unlock the requested partition if locked using two-step sequence */
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writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
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writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
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}
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bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data)
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{
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if (strncmp(data->header, K3_ROM_BOOT_HEADER_MAGIC, 7))
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return false;
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return data->num_components > 1;
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}
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_K3_EARLY_CONS
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int early_console_init(void)
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{
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struct udevice *dev;
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int ret;
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gd->baudrate = CONFIG_BAUDRATE;
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ret = uclass_get_device_by_seq(UCLASS_SERIAL, CONFIG_K3_EARLY_CONS_IDX,
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&dev);
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if (ret) {
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printf("Error getting serial dev for early console! (%d)\n",
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ret);
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return ret;
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}
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gd->cur_serial_dev = dev;
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gd->flags |= GD_FLG_SERIAL_READY;
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gd->have_console = 1;
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return 0;
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}
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#endif
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#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)
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void init_env(void)
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{
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#ifdef CONFIG_SPL_ENV_SUPPORT
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char *part;
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env_init();
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env_relocate();
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switch (spl_boot_device()) {
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case BOOT_DEVICE_MMC2:
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part = env_get("bootpart");
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env_set("storage_interface", "mmc");
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env_set("fw_dev_part", part);
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break;
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case BOOT_DEVICE_SPI:
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env_set("storage_interface", "ubi");
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env_set("fw_ubi_mtdpart", "UBI");
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env_set("fw_ubi_volume", "UBI0");
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break;
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default:
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printf("%s from device %u not supported!\n",
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__func__, spl_boot_device());
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return;
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}
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#endif
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}
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#ifdef CONFIG_FS_LOADER
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int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr)
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{
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struct udevice *fsdev;
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char *name = NULL;
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int size = 0;
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*loadaddr = 0;
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#ifdef CONFIG_SPL_ENV_SUPPORT
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switch (spl_boot_device()) {
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case BOOT_DEVICE_MMC2:
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name = env_get(name_fw);
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*loadaddr = env_get_hex(name_loadaddr, *loadaddr);
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break;
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default:
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printf("Loading rproc fw image from device %u not supported!\n",
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spl_boot_device());
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return 0;
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}
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#endif
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if (!*loadaddr)
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return 0;
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if (!uclass_get_device(UCLASS_FS_FIRMWARE_LOADER, 0, &fsdev)) {
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size = request_firmware_into_buf(fsdev, name, (void *)*loadaddr,
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0, 0);
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}
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return size;
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}
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#else
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int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr)
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{
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return 0;
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}
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#endif
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__weak void release_resources_for_core_shutdown(void)
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{
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debug("%s not implemented...\n", __func__);
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}
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void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
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{
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typedef void __noreturn (*image_entry_noargs_t)(void);
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struct ti_sci_handle *ti_sci = get_ti_sci_handle();
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u32 loadaddr = 0;
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int ret, size = 0, shut_cpu = 0;
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/* Release all the exclusive devices held by SPL before starting ATF */
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ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci);
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ret = rproc_init();
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if (ret)
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panic("rproc failed to be initialized (%d)\n", ret);
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init_env();
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if (!fit_image_info[IMAGE_ID_DM_FW].image_start) {
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size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
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&loadaddr);
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}
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/*
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* It is assumed that remoteproc device 1 is the corresponding
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* Cortex-A core which runs ATF. Make sure DT reflects the same.
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*/
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if (!fit_image_info[IMAGE_ID_ATF].image_start)
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fit_image_info[IMAGE_ID_ATF].image_start =
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spl_image->entry_point;
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ret = rproc_load(1, fit_image_info[IMAGE_ID_ATF].image_start, 0x200);
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if (ret)
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panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret);
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if (!fit_image_info[IMAGE_ID_DM_FW].image_len &&
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!(size > 0 && valid_elf_image(loadaddr))) {
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shut_cpu = 1;
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goto start_arm64;
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}
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if (!fit_image_info[IMAGE_ID_DM_FW].image_start) {
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loadaddr = load_elf_image_phdr(loadaddr);
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} else {
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loadaddr = fit_image_info[IMAGE_ID_DM_FW].image_start;
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if (valid_elf_image(loadaddr))
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loadaddr = load_elf_image_phdr(loadaddr);
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}
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debug("%s: jumping to address %x\n", __func__, loadaddr);
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start_arm64:
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/* Add an extra newline to differentiate the ATF logs from SPL */
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printf("Starting ATF on ARM64 core...\n\n");
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ret = rproc_start(1);
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if (ret)
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panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret);
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if (shut_cpu) {
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debug("Shutting down...\n");
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release_resources_for_core_shutdown();
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while (1)
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asm volatile("wfe");
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}
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image_entry_noargs_t image_entry = (image_entry_noargs_t)loadaddr;
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image_entry();
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}
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#endif
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#if CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS)
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void board_fit_image_post_process(const void *fit, int node, void **p_image,
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size_t *p_size)
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{
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#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)
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int len;
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int i;
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const char *os;
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u32 addr;
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os = fdt_getprop(fit, node, "os", &len);
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addr = fdt_getprop_u32_default_node(fit, node, 0, "entry", -1);
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debug("%s: processing image: addr=%x, size=%d, os=%s\n", __func__,
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addr, *p_size, os);
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for (i = 0; i < IMAGE_AMT; i++) {
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if (!strcmp(os, image_os_match[i])) {
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fit_image_info[i].image_start = addr;
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fit_image_info[i].image_len = *p_size;
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debug("%s: matched image for ID %d\n", __func__, i);
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break;
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}
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}
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#endif
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#if IS_ENABLED(CONFIG_TI_SECURE_DEVICE)
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ti_secure_image_post_process(p_image, p_size);
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#endif
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}
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#endif
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#if defined(CONFIG_OF_LIBFDT)
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int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name)
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{
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u64 msmc_start = 0, msmc_end = 0, msmc_size, reg[2];
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struct ti_sci_handle *ti_sci = get_ti_sci_handle();
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int ret, node, subnode, len, prev_node;
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u32 range[4], addr, size;
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const fdt32_t *sub_reg;
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ti_sci->ops.core_ops.query_msmc(ti_sci, &msmc_start, &msmc_end);
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msmc_size = msmc_end - msmc_start + 1;
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debug("%s: msmc_start = 0x%llx, msmc_size = 0x%llx\n", __func__,
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msmc_start, msmc_size);
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/* find or create "msmc_sram node */
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ret = fdt_path_offset(blob, parent_path);
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if (ret < 0)
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return ret;
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node = fdt_find_or_add_subnode(blob, ret, node_name);
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if (node < 0)
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return node;
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ret = fdt_setprop_string(blob, node, "compatible", "mmio-sram");
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if (ret < 0)
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return ret;
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reg[0] = cpu_to_fdt64(msmc_start);
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reg[1] = cpu_to_fdt64(msmc_size);
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ret = fdt_setprop(blob, node, "reg", reg, sizeof(reg));
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if (ret < 0)
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return ret;
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fdt_setprop_cell(blob, node, "#address-cells", 1);
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fdt_setprop_cell(blob, node, "#size-cells", 1);
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range[0] = 0;
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range[1] = cpu_to_fdt32(msmc_start >> 32);
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range[2] = cpu_to_fdt32(msmc_start & 0xffffffff);
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range[3] = cpu_to_fdt32(msmc_size);
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ret = fdt_setprop(blob, node, "ranges", range, sizeof(range));
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if (ret < 0)
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return ret;
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subnode = fdt_first_subnode(blob, node);
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prev_node = 0;
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/* Look for invalid subnodes and delete them */
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while (subnode >= 0) {
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sub_reg = fdt_getprop(blob, subnode, "reg", &len);
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addr = fdt_read_number(sub_reg, 1);
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sub_reg++;
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size = fdt_read_number(sub_reg, 1);
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debug("%s: subnode = %d, addr = 0x%x. size = 0x%x\n", __func__,
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subnode, addr, size);
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if (addr + size > msmc_size ||
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!strncmp(fdt_get_name(blob, subnode, &len), "sysfw", 5) ||
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!strncmp(fdt_get_name(blob, subnode, &len), "l3cache", 7)) {
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fdt_del_node(blob, subnode);
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debug("%s: deleting subnode %d\n", __func__, subnode);
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if (!prev_node)
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subnode = fdt_first_subnode(blob, node);
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else
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subnode = fdt_next_subnode(blob, prev_node);
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} else {
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prev_node = subnode;
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subnode = fdt_next_subnode(blob, prev_node);
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}
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}
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return 0;
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}
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int fdt_disable_node(void *blob, char *node_path)
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{
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int offs;
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int ret;
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offs = fdt_path_offset(blob, node_path);
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if (offs < 0) {
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printf("Node %s not found.\n", node_path);
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return offs;
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}
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ret = fdt_setprop_string(blob, offs, "status", "disabled");
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if (ret < 0) {
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printf("Could not add status property to node %s: %s\n",
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node_path, fdt_strerror(ret));
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return ret;
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}
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return 0;
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}
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#endif
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#ifndef CONFIG_SYSRESET
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void reset_cpu(void)
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{
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}
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#endif
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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struct udevice *soc;
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char name[64];
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int ret;
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printf("SoC: ");
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ret = soc_get(&soc);
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if (ret) {
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printf("UNKNOWN\n");
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return 0;
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}
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ret = soc_get_family(soc, name, 64);
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if (!ret) {
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printf("%s ", name);
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}
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ret = soc_get_revision(soc, name, 64);
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if (!ret) {
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printf("%s\n", name);
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}
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return 0;
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}
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#endif
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bool soc_is_j721e(void)
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{
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u32 soc;
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soc = (readl(CTRLMMR_WKUP_JTAG_ID) &
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JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
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return soc == J721E;
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}
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bool soc_is_j7200(void)
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{
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u32 soc;
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soc = (readl(CTRLMMR_WKUP_JTAG_ID) &
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JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
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return soc == J7200;
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}
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#ifdef CONFIG_ARM64
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void board_prep_linux(bootm_headers_t *images)
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{
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debug("Linux kernel Image start = 0x%lx end = 0x%lx\n",
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images->os.start, images->os.end);
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__asm_flush_dcache_range(images->os.start,
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ROUND(images->os.end,
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CONFIG_SYS_CACHELINE_SIZE));
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}
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#endif
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#ifdef CONFIG_CPU_V7R
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void disable_linefill_optimization(void)
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{
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u32 actlr;
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/*
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* On K3 devices there are 2 conditions where R5F can deadlock:
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* 1.When software is performing series of store operations to
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* cacheable write back/write allocate memory region and later
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* on software execute barrier operation (DSB or DMB). R5F may
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* hang at the barrier instruction.
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* 2.When software is performing a mix of load and store operations
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* within a tight loop and store operations are all writing to
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* cacheable write back/write allocates memory regions, R5F may
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* hang at one of the load instruction.
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*
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* To avoid the above two conditions disable linefill optimization
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* inside Cortex R5F.
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*/
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asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr));
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actlr |= (1 << 13); /* Set DLFO bit */
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asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr));
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}
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#endif
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void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size)
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{
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struct ti_sci_msg_fwl_region region;
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struct ti_sci_fwl_ops *fwl_ops;
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struct ti_sci_handle *ti_sci;
|
|
size_t i, j;
|
|
|
|
ti_sci = get_ti_sci_handle();
|
|
fwl_ops = &ti_sci->ops.fwl_ops;
|
|
for (i = 0; i < fwl_data_size; i++) {
|
|
for (j = 0; j < fwl_data[i].regions; j++) {
|
|
region.fwl_id = fwl_data[i].fwl_id;
|
|
region.region = j;
|
|
region.n_permission_regs = 3;
|
|
|
|
fwl_ops->get_fwl_region(ti_sci, ®ion);
|
|
|
|
if (region.control != 0) {
|
|
pr_debug("Attempting to disable firewall %5d (%25s)\n",
|
|
region.fwl_id, fwl_data[i].name);
|
|
region.control = 0;
|
|
|
|
if (fwl_ops->set_fwl_region(ti_sci, ®ion))
|
|
pr_err("Could not disable firewall %5d (%25s)\n",
|
|
region.fwl_id, fwl_data[i].name);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void spl_enable_dcache(void)
|
|
{
|
|
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
|
|
phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE;
|
|
|
|
dram_init_banksize();
|
|
|
|
/* reserve TLB table */
|
|
gd->arch.tlb_size = PGTABLE_SIZE;
|
|
|
|
ram_top += get_effective_memsize();
|
|
/* keep ram_top in the 32-bit address space */
|
|
if (ram_top >= 0x100000000)
|
|
ram_top = (phys_addr_t) 0x100000000;
|
|
|
|
gd->arch.tlb_addr = ram_top - gd->arch.tlb_size;
|
|
debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
|
|
gd->arch.tlb_addr + gd->arch.tlb_size);
|
|
|
|
dcache_enable();
|
|
#endif
|
|
}
|
|
|
|
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
|
|
void spl_board_prepare_for_boot(void)
|
|
{
|
|
dcache_disable();
|
|
}
|
|
|
|
void spl_board_prepare_for_linux(void)
|
|
{
|
|
dcache_disable();
|
|
}
|
|
#endif
|