mirror of
https://github.com/AsahiLinux/u-boot
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d024236e5a
We have a large number of places where while we historically referenced gd in the code we no longer do, as well as cases where the code added that line "just in case" during development and never dropped it. Signed-off-by: Tom Rini <trini@konsulko.com>
87 lines
1.8 KiB
C
87 lines
1.8 KiB
C
/*
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* Copyright (C) 2016 Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <linux/libfdt.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <asm/armv8/mmu.h>
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/* Armada 3700 */
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#define MVEBU_GPIO_NB_REG_BASE (MVEBU_REGISTER(0x13800))
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#define MVEBU_TEST_PIN_LATCH_N (MVEBU_GPIO_NB_REG_BASE + 0x8)
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#define MVEBU_XTAL_MODE_MASK BIT(9)
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#define MVEBU_XTAL_MODE_OFFS 9
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#define MVEBU_XTAL_CLOCK_25MHZ 0x0
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#define MVEBU_XTAL_CLOCK_40MHZ 0x1
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#define MVEBU_NB_WARM_RST_REG (MVEBU_GPIO_NB_REG_BASE + 0x40)
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#define MVEBU_NB_WARM_RST_MAGIC_NUM 0x1d1e
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static struct mm_region mvebu_mem_map[] = {
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{
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/* RAM */
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.phys = 0x0UL,
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.virt = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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},
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{
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/* SRAM, MMIO regions */
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.phys = 0xd0000000UL,
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.virt = 0xd0000000UL,
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.size = 0x02000000UL, /* 32MiB internal registers */
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE
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},
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{
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/* PCI regions */
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.phys = 0xe8000000UL,
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.virt = 0xe8000000UL,
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.size = 0x02000000UL, /* 32MiB master PCI space */
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE
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},
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{
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = mvebu_mem_map;
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void reset_cpu(ulong ignored)
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{
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/*
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* Write magic number of 0x1d1e to North Bridge Warm Reset register
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* to trigger warm reset
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*/
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writel(MVEBU_NB_WARM_RST_MAGIC_NUM, MVEBU_NB_WARM_RST_REG);
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}
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/*
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* get_ref_clk
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*
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* return: reference clock in MHz (25 or 40)
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*/
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u32 get_ref_clk(void)
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{
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u32 regval;
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regval = (readl(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >>
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MVEBU_XTAL_MODE_OFFS;
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if (regval == MVEBU_XTAL_CLOCK_25MHZ)
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return 25;
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else
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return 40;
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}
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