mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 00:47:26 +00:00
335 lines
6.2 KiB
ArmAsm
335 lines
6.2 KiB
ArmAsm
/*
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* (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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* (C) Copyright 2011, Julius Baxter <julius@opencores.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <asm-offsets.h>
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#include <asm/spr-defs.h>
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#define EXCEPTION_STACK_SIZE (128+128)
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#define HANDLE_EXCEPTION \
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l.addi r1, r1, -EXCEPTION_STACK_SIZE ;\
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l.sw 0x1c(r1), r9 ;\
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l.jal _exception_handler ;\
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l.nop ;\
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l.lwz r9, 0x1c(r1) ;\
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l.addi r1, r1, EXCEPTION_STACK_SIZE ;\
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l.rfe ;\
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l.nop
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.section .vectors, "ax"
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.global __reset
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/* reset */
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.org 0x100
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__reset:
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/* there is no guarantee r0 is hardwired to zero, clear it here */
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l.andi r0, r0, 0
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/* reset stack and frame pointers */
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l.andi r1, r0, 0
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l.andi r2, r0, 0
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/* set supervisor mode */
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l.ori r3,r0,SPR_SR_SM
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l.mtspr r0,r3,SPR_SR
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/* Relocate u-boot */
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l.movhi r3,hi(__start) /* source start address */
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l.ori r3,r3,lo(__start)
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l.movhi r4,hi(_stext) /* dest start address */
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l.ori r4,r4,lo(_stext)
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l.movhi r5,hi(__end) /* dest end address */
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l.ori r5,r5,lo(__end)
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.L_reloc:
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l.lwz r6,0(r3)
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l.sw 0(r4),r6
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l.addi r3,r3,4
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l.sfltu r4,r5
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l.bf .L_reloc
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l.addi r4,r4,4 /* delay slot */
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#ifdef CONFIG_SYS_RELOCATE_VECTORS
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/* Relocate vectors from 0xf0000000 to 0x00000000 */
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l.movhi r4, 0xf000 /* source */
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l.movhi r5, 0 /* destination */
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l.addi r6, r5, CONFIG_SYS_VECTORS_LEN /* length */
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.L_relocvectors:
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l.lwz r7, 0(r4)
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l.sw 0(r5), r7
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l.addi r5, r5, 4
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l.sfeq r5,r6
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l.bnf .L_relocvectors
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l.addi r4,r4, 4
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#endif
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l.j _start
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l.nop
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/* bus error */
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.org 0x200
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HANDLE_EXCEPTION
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/* data page fault */
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.org 0x300
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HANDLE_EXCEPTION
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/* instruction page fault */
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.org 0x400
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HANDLE_EXCEPTION
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/* tick timer */
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.org 0x500
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HANDLE_EXCEPTION
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/* alignment */
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.org 0x600
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HANDLE_EXCEPTION
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/* illegal instruction */
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.org 0x700
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HANDLE_EXCEPTION
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/* external interrupt */
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.org 0x800
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HANDLE_EXCEPTION
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/* D-TLB miss */
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.org 0x900
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HANDLE_EXCEPTION
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/* I-TLB miss */
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.org 0xa00
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HANDLE_EXCEPTION
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/* range */
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.org 0xb00
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HANDLE_EXCEPTION
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/* system call */
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.org 0xc00
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HANDLE_EXCEPTION
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/* floating point */
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.org 0xd00
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HANDLE_EXCEPTION
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/* trap */
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.org 0xe00
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HANDLE_EXCEPTION
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/* reserved */
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.org 0xf00
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HANDLE_EXCEPTION
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/* reserved */
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.org 0x1100
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HANDLE_EXCEPTION
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/* reserved */
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.org 0x1200
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HANDLE_EXCEPTION
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/* reserved */
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.org 0x1300
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HANDLE_EXCEPTION
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/* reserved */
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.org 0x1400
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HANDLE_EXCEPTION
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/* reserved */
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.org 0x1500
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HANDLE_EXCEPTION
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/* reserved */
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.org 0x1600
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HANDLE_EXCEPTION
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/* reserved */
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.org 0x1700
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HANDLE_EXCEPTION
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/* reserved */
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.org 0x1800
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HANDLE_EXCEPTION
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/* reserved */
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.org 0x1900
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HANDLE_EXCEPTION
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/* reserved */
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.org 0x1a00
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HANDLE_EXCEPTION
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/* reserved */
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.org 0x1b00
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HANDLE_EXCEPTION
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/* reserved */
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.org 0x1c00
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HANDLE_EXCEPTION
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/* reserved */
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.org 0x1d00
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HANDLE_EXCEPTION
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/* reserved */
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.org 0x1e00
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HANDLE_EXCEPTION
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/* reserved */
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.org 0x1f00
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HANDLE_EXCEPTION
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/* Startup routine */
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.text
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.global _start
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_start:
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/* Init stack and frame pointers */
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l.movhi r1, hi(CONFIG_SYS_INIT_SP_ADDR)
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l.ori r1, r1, lo(CONFIG_SYS_INIT_SP_ADDR)
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l.or r2, r0, r1
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/* clear BSS segments */
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l.movhi r4, hi(_bss_start)
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l.ori r4, r4, lo(_bss_start)
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l.movhi r5, hi(_bss_end)
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l.ori r5, r5, lo(_bss_end)
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.L_clear_bss:
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l.sw 0(r4), r0
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l.sfltu r4,r5
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l.bf .L_clear_bss
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l.addi r4,r4,4
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/* Reset registers before jumping to board_init */
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l.andi r3, r0, 0
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l.andi r4, r0, 0
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l.andi r5, r0, 0
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l.andi r6, r0, 0
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l.andi r7, r0, 0
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l.andi r8, r0, 0
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l.andi r9, r0, 0
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l.andi r10, r0, 0
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l.andi r11, r0, 0
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l.andi r12, r0, 0
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l.andi r13, r0, 0
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l.andi r14, r0, 0
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l.andi r15, r0, 0
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l.andi r17, r0, 0
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l.andi r18, r0, 0
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l.andi r19, r0, 0
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l.andi r20, r0, 0
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l.andi r21, r0, 0
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l.andi r22, r0, 0
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l.andi r23, r0, 0
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l.andi r24, r0, 0
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l.andi r25, r0, 0
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l.andi r26, r0, 0
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l.andi r27, r0, 0
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l.andi r28, r0, 0
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l.andi r29, r0, 0
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l.andi r30, r0, 0
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l.andi r31, r0, 0
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l.j board_init
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l.nop
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.size _start, .-_start
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/*
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* Store state onto stack and call the real exception handler
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*/
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.section .text
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.extern exception_handler
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.type _exception_handler,@function
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_exception_handler:
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/* Store state (r9 already saved)*/
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l.sw 0x00(r1), r2
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l.sw 0x04(r1), r3
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l.sw 0x08(r1), r4
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l.sw 0x0c(r1), r5
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l.sw 0x10(r1), r6
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l.sw 0x14(r1), r7
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l.sw 0x18(r1), r8
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l.sw 0x20(r1), r10
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l.sw 0x24(r1), r11
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l.sw 0x28(r1), r12
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l.sw 0x2c(r1), r13
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l.sw 0x30(r1), r14
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l.sw 0x34(r1), r15
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l.sw 0x38(r1), r16
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l.sw 0x3c(r1), r17
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l.sw 0x40(r1), r18
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l.sw 0x44(r1), r19
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l.sw 0x48(r1), r20
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l.sw 0x4c(r1), r21
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l.sw 0x50(r1), r22
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l.sw 0x54(r1), r23
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l.sw 0x58(r1), r24
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l.sw 0x5c(r1), r25
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l.sw 0x60(r1), r26
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l.sw 0x64(r1), r27
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l.sw 0x68(r1), r28
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l.sw 0x6c(r1), r29
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l.sw 0x70(r1), r30
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l.sw 0x74(r1), r31
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/* Save return address */
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l.or r14, r0, r9
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/* Call exception handler with the link address as argument */
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l.jal exception_handler
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l.or r3, r0, r14
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/* Load return address */
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l.or r9, r0, r14
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/* Restore state */
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l.lwz r2, 0x00(r1)
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l.lwz r3, 0x04(r1)
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l.lwz r4, 0x08(r1)
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l.lwz r5, 0x0c(r1)
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l.lwz r6, 0x10(r1)
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l.lwz r7, 0x14(r1)
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l.lwz r8, 0x18(r1)
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l.lwz r10, 0x20(r1)
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l.lwz r11, 0x24(r1)
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l.lwz r12, 0x28(r1)
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l.lwz r13, 0x2c(r1)
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l.lwz r14, 0x30(r1)
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l.lwz r15, 0x34(r1)
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l.lwz r16, 0x38(r1)
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l.lwz r17, 0x3c(r1)
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l.lwz r18, 0x40(r1)
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l.lwz r19, 0x44(r1)
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l.lwz r20, 0x48(r1)
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l.lwz r21, 0x4c(r1)
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l.lwz r22, 0x50(r1)
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l.lwz r23, 0x54(r1)
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l.lwz r24, 0x58(r1)
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l.lwz r25, 0x5c(r1)
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l.lwz r26, 0x60(r1)
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l.lwz r27, 0x64(r1)
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l.lwz r28, 0x68(r1)
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l.lwz r29, 0x6c(r1)
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l.lwz r30, 0x70(r1)
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l.lwz r31, 0x74(r1)
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l.jr r9
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l.nop
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