mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 18:59:44 +00:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
480 lines
15 KiB
C
480 lines
15 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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* (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com>
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*/
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#ifndef _IMX_REGS_H
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#define _IMX_REGS_H
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#include <asm/arch/regs-rtc.h>
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#ifndef __ASSEMBLY__
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extern void imx_gpio_mode (int gpio_mode);
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#ifdef CONFIG_MXC_UART
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extern void mx27_uart1_init_pins(void);
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#endif /* CONFIG_MXC_UART */
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#ifdef CONFIG_FEC_MXC
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extern void mx27_fec_init_pins(void);
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#endif /* CONFIG_FEC_MXC */
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#ifdef CONFIG_MMC_MXC
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extern void mx27_sd1_init_pins(void);
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extern void mx27_sd2_init_pins(void);
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#endif /* CONFIG_MMC_MXC */
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/* AIPI */
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struct aipi_regs {
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u32 psr0;
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u32 psr1;
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};
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/* System Control */
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struct system_control_regs {
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u32 res[5];
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u32 fmcr;
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u32 gpcr;
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u32 wbcr;
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u32 dscr1;
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u32 dscr2;
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u32 dscr3;
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u32 dscr4;
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u32 dscr5;
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u32 dscr6;
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u32 dscr7;
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u32 dscr8;
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u32 dscr9;
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u32 dscr10;
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u32 dscr11;
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u32 dscr12;
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u32 dscr13;
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u32 pscr;
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u32 pmcr;
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u32 res1;
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u32 dcvr0;
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u32 dcvr1;
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u32 dcvr2;
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u32 dcvr3;
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};
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/* Chip Select Registers */
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struct weim_regs {
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u32 cs0u; /* Chip Select 0 Upper Register */
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u32 cs0l; /* Chip Select 0 Lower Register */
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u32 cs0a; /* Chip Select 0 Addition Register */
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u32 pad0;
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u32 cs1u; /* Chip Select 1 Upper Register */
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u32 cs1l; /* Chip Select 1 Lower Register */
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u32 cs1a; /* Chip Select 1 Addition Register */
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u32 pad1;
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u32 cs2u; /* Chip Select 2 Upper Register */
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u32 cs2l; /* Chip Select 2 Lower Register */
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u32 cs2a; /* Chip Select 2 Addition Register */
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u32 pad2;
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u32 cs3u; /* Chip Select 3 Upper Register */
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u32 cs3l; /* Chip Select 3 Lower Register */
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u32 cs3a; /* Chip Select 3 Addition Register */
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u32 pad3;
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u32 cs4u; /* Chip Select 4 Upper Register */
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u32 cs4l; /* Chip Select 4 Lower Register */
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u32 cs4a; /* Chip Select 4 Addition Register */
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u32 pad4;
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u32 cs5u; /* Chip Select 5 Upper Register */
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u32 cs5l; /* Chip Select 5 Lower Register */
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u32 cs5a; /* Chip Select 5 Addition Register */
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u32 pad5;
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u32 eim; /* WEIM Configuration Register */
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};
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/* SDRAM Controller registers */
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struct esdramc_regs {
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/* Enhanced SDRAM Control Register 0 */
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u32 esdctl0;
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/* Enhanced SDRAM Configuration Register 0 */
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u32 esdcfg0;
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/* Enhanced SDRAM Control Register 1 */
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u32 esdctl1;
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/* Enhanced SDRAM Configuration Register 1 */
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u32 esdcfg1;
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/* Enhanced SDRAM Miscellanious Register */
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u32 esdmisc;
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};
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/* Watchdog Registers*/
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struct wdog_regs {
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u16 wcr;
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u16 wsr;
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u16 wstr;
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};
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/* PLL registers */
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struct pll_regs {
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u32 cscr; /* Clock Source Control Register */
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u32 mpctl0; /* MCU PLL Control Register 0 */
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u32 mpctl1; /* MCU PLL Control Register 1 */
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u32 spctl0; /* System PLL Control Register 0 */
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u32 spctl1; /* System PLL Control Register 1 */
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u32 osc26mctl; /* Oscillator 26M Register */
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u32 pcdr0; /* Peripheral Clock Divider Register 0 */
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u32 pcdr1; /* Peripheral Clock Divider Register 1 */
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u32 pccr0; /* Peripheral Clock Control Register 0 */
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u32 pccr1; /* Peripheral Clock Control Register 1 */
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u32 ccsr; /* Clock Control Status Register */
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};
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/*
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* Definitions for the clocksource registers
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*/
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struct gpt_regs {
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u32 gpt_tctl;
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u32 gpt_tprer;
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u32 gpt_tcmp;
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u32 gpt_tcr;
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u32 gpt_tcn;
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u32 gpt_tstat;
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};
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/* IIM Control Registers */
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struct iim_regs {
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u32 iim_stat;
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u32 iim_statm;
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u32 iim_err;
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u32 iim_emask;
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u32 iim_fctl;
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u32 iim_ua;
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u32 iim_la;
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u32 iim_sdat;
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u32 iim_prev;
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u32 iim_srev;
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u32 iim_prg_p;
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u32 iim_scs0;
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u32 iim_scs1;
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u32 iim_scs2;
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u32 iim_scs3;
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u32 res[0x1f1];
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struct fuse_bank {
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u32 fuse_regs[0x20];
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u32 fuse_rsvd[0xe0];
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} bank[2];
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};
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struct fuse_bank0_regs {
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u32 fuse0_3[5];
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u32 mac_addr[6];
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u32 fuse10_31[0x16];
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};
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#endif
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#define ARCH_MXC
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#define IMX_IO_BASE 0x10000000
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#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE)
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#define IMX_WDT_BASE (0x02000 + IMX_IO_BASE)
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#define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE)
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#define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE)
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#define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE)
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#define IMX_RTC_BASE (0x07000 + IMX_IO_BASE)
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#define UART1_BASE (0x0a000 + IMX_IO_BASE)
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#define UART2_BASE (0x0b000 + IMX_IO_BASE)
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#define UART3_BASE (0x0c000 + IMX_IO_BASE)
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#define UART4_BASE (0x0d000 + IMX_IO_BASE)
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#define I2C1_BASE_ADDR (0x12000 + IMX_IO_BASE)
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#define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE)
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#define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE)
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#define IMX_TIM5_BASE (0x1a000 + IMX_IO_BASE)
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#define IMX_UART5_BASE (0x1b000 + IMX_IO_BASE)
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#define IMX_UART6_BASE (0x1c000 + IMX_IO_BASE)
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#define I2C2_BASE_ADDR (0x1D000 + IMX_IO_BASE)
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#define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE)
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#define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE)
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#define IMX_PLL_BASE (0x27000 + IMX_IO_BASE)
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#define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE)
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#define IMX_IIM_BASE (0x28000 + IMX_IO_BASE)
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#define IIM_BASE_ADDR IMX_IIM_BASE
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#define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE)
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#define IMX_NFC_BASE (0xD8000000)
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#define IMX_ESD_BASE (0xD8001000)
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#define IMX_WEIM_BASE (0xD8002000)
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#define NFC_BASE_ADDR IMX_NFC_BASE
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/* FMCR System Control bit definition*/
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#define UART4_RXD_CTL (1 << 25)
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#define UART4_RTS_CTL (1 << 24)
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#define KP_COL6_CTL (1 << 18)
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#define KP_ROW7_CTL (1 << 17)
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#define KP_ROW6_CTL (1 << 16)
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#define PC_WAIT_B_CTL (1 << 14)
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#define PC_READY_CTL (1 << 13)
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#define PC_VS1_CTL (1 << 12)
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#define PC_VS2_CTL (1 << 11)
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#define PC_BVD1_CTL (1 << 10)
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#define PC_BVD2_CTL (1 << 9)
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#define IOS16_CTL (1 << 8)
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#define NF_FMS (1 << 5)
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#define NF_16BIT_SEL (1 << 4)
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#define SLCDC_SEL (1 << 2)
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#define SDCS1_SEL (1 << 1)
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#define SDCS0_SEL (1 << 0)
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/* important definition of some bits of WCR */
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#define WCR_WDE 0x04
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#define CSCR_MPEN (1 << 0)
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#define CSCR_SPEN (1 << 1)
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#define CSCR_FPM_EN (1 << 2)
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#define CSCR_OSC26M_DIS (1 << 3)
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#define CSCR_OSC26M_DIV1P5 (1 << 4)
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#define CSCR_AHB_DIV
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#define CSCR_ARM_DIV
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#define CSCR_ARM_SRC_MPLL (1 << 15)
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#define CSCR_MCU_SEL (1 << 16)
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#define CSCR_SP_SEL (1 << 17)
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#define CSCR_MPLL_RESTART (1 << 18)
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#define CSCR_SPLL_RESTART (1 << 19)
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#define CSCR_MSHC_SEL (1 << 20)
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#define CSCR_H264_SEL (1 << 21)
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#define CSCR_SSI1_SEL (1 << 22)
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#define CSCR_SSI2_SEL (1 << 23)
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#define CSCR_SD_CNT
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#define CSCR_USB_DIV
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#define CSCR_UPDATE_DIS (1 << 31)
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#define MPCTL1_BRMO (1 << 6)
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#define MPCTL1_LF (1 << 15)
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#define PCCR0_SSI2_EN (1 << 0)
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#define PCCR0_SSI1_EN (1 << 1)
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#define PCCR0_SLCDC_EN (1 << 2)
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#define PCCR0_SDHC3_EN (1 << 3)
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#define PCCR0_SDHC2_EN (1 << 4)
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#define PCCR0_SDHC1_EN (1 << 5)
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#define PCCR0_SDC_EN (1 << 6)
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#define PCCR0_SAHARA_EN (1 << 7)
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#define PCCR0_RTIC_EN (1 << 8)
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#define PCCR0_RTC_EN (1 << 9)
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#define PCCR0_PWM_EN (1 << 11)
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#define PCCR0_OWIRE_EN (1 << 12)
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#define PCCR0_MSHC_EN (1 << 13)
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#define PCCR0_LCDC_EN (1 << 14)
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#define PCCR0_KPP_EN (1 << 15)
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#define PCCR0_IIM_EN (1 << 16)
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#define PCCR0_I2C2_EN (1 << 17)
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#define PCCR0_I2C1_EN (1 << 18)
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#define PCCR0_GPT6_EN (1 << 19)
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#define PCCR0_GPT5_EN (1 << 20)
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#define PCCR0_GPT4_EN (1 << 21)
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#define PCCR0_GPT3_EN (1 << 22)
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#define PCCR0_GPT2_EN (1 << 23)
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#define PCCR0_GPT1_EN (1 << 24)
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#define PCCR0_GPIO_EN (1 << 25)
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#define PCCR0_FEC_EN (1 << 26)
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#define PCCR0_EMMA_EN (1 << 27)
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#define PCCR0_DMA_EN (1 << 28)
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#define PCCR0_CSPI3_EN (1 << 29)
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#define PCCR0_CSPI2_EN (1 << 30)
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#define PCCR0_CSPI1_EN (1 << 31)
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#define PCCR1_MSHC_BAUDEN (1 << 2)
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#define PCCR1_NFC_BAUDEN (1 << 3)
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#define PCCR1_SSI2_BAUDEN (1 << 4)
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#define PCCR1_SSI1_BAUDEN (1 << 5)
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#define PCCR1_H264_BAUDEN (1 << 6)
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#define PCCR1_PERCLK4_EN (1 << 7)
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#define PCCR1_PERCLK3_EN (1 << 8)
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#define PCCR1_PERCLK2_EN (1 << 9)
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#define PCCR1_PERCLK1_EN (1 << 10)
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#define PCCR1_HCLK_USB (1 << 11)
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#define PCCR1_HCLK_SLCDC (1 << 12)
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#define PCCR1_HCLK_SAHARA (1 << 13)
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#define PCCR1_HCLK_RTIC (1 << 14)
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#define PCCR1_HCLK_LCDC (1 << 15)
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#define PCCR1_HCLK_H264 (1 << 16)
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#define PCCR1_HCLK_FEC (1 << 17)
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#define PCCR1_HCLK_EMMA (1 << 18)
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#define PCCR1_HCLK_EMI (1 << 19)
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#define PCCR1_HCLK_DMA (1 << 20)
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#define PCCR1_HCLK_CSI (1 << 21)
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#define PCCR1_HCLK_BROM (1 << 22)
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#define PCCR1_HCLK_ATA (1 << 23)
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#define PCCR1_WDT_EN (1 << 24)
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#define PCCR1_USB_EN (1 << 25)
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#define PCCR1_UART6_EN (1 << 26)
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#define PCCR1_UART5_EN (1 << 27)
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#define PCCR1_UART4_EN (1 << 28)
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#define PCCR1_UART3_EN (1 << 29)
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#define PCCR1_UART2_EN (1 << 30)
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#define PCCR1_UART1_EN (1 << 31)
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/* SDRAM Controller registers bitfields */
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#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0)
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#define ESDCTL_BL (1 << 7)
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#define ESDCTL_FP (1 << 8)
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#define ESDCTL_PWDT(x) (((x) & 3) << 10)
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#define ESDCTL_SREFR(x) (((x) & 7) << 13)
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#define ESDCTL_DSIZ_16_UPPER (0 << 16)
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#define ESDCTL_DSIZ_16_LOWER (1 << 16)
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#define ESDCTL_DSIZ_32 (2 << 16)
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#define ESDCTL_COL8 (0 << 20)
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#define ESDCTL_COL9 (1 << 20)
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#define ESDCTL_COL10 (2 << 20)
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#define ESDCTL_ROW11 (0 << 24)
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#define ESDCTL_ROW12 (1 << 24)
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#define ESDCTL_ROW13 (2 << 24)
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#define ESDCTL_ROW14 (3 << 24)
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#define ESDCTL_ROW15 (4 << 24)
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#define ESDCTL_SP (1 << 27)
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#define ESDCTL_SMODE_NORMAL (0 << 28)
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#define ESDCTL_SMODE_PRECHARGE (1 << 28)
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#define ESDCTL_SMODE_AUTO_REF (2 << 28)
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#define ESDCTL_SMODE_LOAD_MODE (3 << 28)
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#define ESDCTL_SMODE_MAN_REF (4 << 28)
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#define ESDCTL_SDE (1 << 31)
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#define ESDCFG_TRC(x) (((x) & 0xf) << 0)
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#define ESDCFG_TRCD(x) (((x) & 0x7) << 4)
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#define ESDCFG_TCAS(x) (((x) & 0x3) << 8)
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#define ESDCFG_TRRD(x) (((x) & 0x3) << 10)
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#define ESDCFG_TRAS(x) (((x) & 0x7) << 12)
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#define ESDCFG_TWR (1 << 15)
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#define ESDCFG_TMRD(x) (((x) & 0x3) << 16)
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#define ESDCFG_TRP(x) (((x) & 0x3) << 18)
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#define ESDCFG_TWTR (1 << 20)
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#define ESDCFG_TXP(x) (((x) & 0x3) << 21)
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#define ESDMISC_RST (1 << 1)
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#define ESDMISC_MDDREN (1 << 2)
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#define ESDMISC_MDDR_DL_RST (1 << 3)
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#define ESDMISC_MDDR_MDIS (1 << 4)
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#define ESDMISC_LHD (1 << 5)
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#define ESDMISC_MA10_SHARE (1 << 6)
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#define ESDMISC_SDRAM_RDY (1 << 31)
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#define PC5_PF_I2C2_DATA (GPIO_PORTC | GPIO_OUT | GPIO_PF | 5)
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#define PC6_PF_I2C2_CLK (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6)
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#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 7)
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#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 8)
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#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9)
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#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 10)
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#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11)
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#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 12)
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#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 13)
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#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0)
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#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1)
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#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2)
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#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3)
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#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4)
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#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5)
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#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6)
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#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7)
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#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_IN | GPIO_AF | 8)
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#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9)
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#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10)
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#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11)
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#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12)
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#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13)
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#define PD14_AOUT_FEC_CLR (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14)
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#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15)
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#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16)
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#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23)
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#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_OUT | GPIO_PF | 0)
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#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_OUT | GPIO_PF | 1)
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#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_OUT | GPIO_PF | 2)
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#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3)
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#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4)
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#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6)
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#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 7)
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#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8)
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#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 9)
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#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10)
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#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 11)
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#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12)
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#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13)
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#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14)
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#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15)
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#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18)
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#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19)
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#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20)
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#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21)
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#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22)
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#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23)
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#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4)
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#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5)
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#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6)
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#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7)
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#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8)
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#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9)
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#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
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#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
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#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 24)
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#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_OUT | GPIO_PF | 25)
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/* Clocksource Bitfields */
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#define TCTL_SWR (1 << 15) /* Software reset */
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#define TCTL_FRR (1 << 8) /* Freerun / restart */
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#define TCTL_CAP (3 << 6) /* Capture Edge */
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#define TCTL_OM (1 << 5) /* output mode */
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#define TCTL_IRQEN (1 << 4) /* interrupt enable */
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#define TCTL_CLKSOURCE 1 /* Clock source bit position */
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#define TCTL_TEN 1 /* Timer enable */
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#define TPRER_PRES 0xff /* Prescale */
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#define TSTAT_CAPT (1 << 1) /* Capture event */
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#define TSTAT_COMP 1 /* Compare event */
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#define GPIO1_BASE_ADDR 0x10015000
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#define GPIO2_BASE_ADDR 0x10015100
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#define GPIO3_BASE_ADDR 0x10015200
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#define GPIO4_BASE_ADDR 0x10015300
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#define GPIO5_BASE_ADDR 0x10015400
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#define GPIO6_BASE_ADDR 0x10015500
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#define GPIO_OUT (1 << 8)
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#define GPIO_IN (0 << 8)
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#define GPIO_PUEN (1 << 9)
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#define GPIO_PF (1 << 10)
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#define GPIO_AF (1 << 11)
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#define GPIO_OCR_SHIFT 12
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#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
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#define GPIO_AIN (0 << GPIO_OCR_SHIFT)
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#define GPIO_BIN (1 << GPIO_OCR_SHIFT)
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#define GPIO_CIN (2 << GPIO_OCR_SHIFT)
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#define GPIO_GPIO (3 << GPIO_OCR_SHIFT)
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#define GPIO_AOUT_SHIFT 14
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#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
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#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT)
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#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
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#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT)
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#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT)
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#define GPIO_BOUT_SHIFT 16
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#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
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#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT)
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#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT)
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#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
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#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
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#define IIM_STAT_BUSY (1 << 7)
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#define IIM_STAT_PRGD (1 << 1)
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#define IIM_STAT_SNSD (1 << 0)
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#define IIM_ERR_PRGE (1 << 7)
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#define IIM_ERR_WPE (1 << 6)
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#define IIM_ERR_OPE (1 << 5)
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#define IIM_ERR_RPE (1 << 4)
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#define IIM_ERR_WLRE (1 << 3)
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#define IIM_ERR_SNSE (1 << 2)
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#define IIM_ERR_PARITYE (1 << 1)
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#endif /* _IMX_REGS_H */
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