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4ebeb4c559
The command "pci bar" and "pci region" display the address and size in 16 characters including "0x", so the command can only display 14 hexadecimal digits if the number of digits in the address and size is less than 14. ID Base Size Width Type ---------------------------------------------------------- 0 0x00000020000000 0x00000000100000 64 MEM Prefetchable 1 0xffff000080000000 0x00000000100000 64 MEM Prefetchable The 64-bit address and size should be displayed in 18(= 16+2) digits, so this patch adjusts them. Cc: Yehuda Yitschak <yehuday@marvell.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
809 lines
21 KiB
C
809 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Andreas Heppel <aheppel@sysgo.de>
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*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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* Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
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*/
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/*
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* PCI routines
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*/
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#include <common.h>
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#include <bootretry.h>
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#include <cli.h>
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#include <command.h>
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#include <console.h>
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#include <dm.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <pci.h>
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struct pci_reg_info {
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const char *name;
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enum pci_size_t size;
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u8 offset;
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};
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static int pci_byte_size(enum pci_size_t size)
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{
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switch (size) {
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case PCI_SIZE_8:
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return 1;
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case PCI_SIZE_16:
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return 2;
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case PCI_SIZE_32:
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default:
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return 4;
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}
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}
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static int pci_field_width(enum pci_size_t size)
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{
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return pci_byte_size(size) * 2;
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}
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#ifdef CONFIG_DM_PCI
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static void pci_show_regs(struct udevice *dev, struct pci_reg_info *regs)
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{
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for (; regs->name; regs++) {
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unsigned long val;
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dm_pci_read_config(dev, regs->offset, &val, regs->size);
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printf(" %s =%*s%#.*lx\n", regs->name,
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(int)(28 - strlen(regs->name)), "",
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pci_field_width(regs->size), val);
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}
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}
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#else
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static unsigned long pci_read_config(pci_dev_t dev, int offset,
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enum pci_size_t size)
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{
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u32 val32;
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u16 val16;
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u8 val8;
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switch (size) {
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case PCI_SIZE_8:
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pci_read_config_byte(dev, offset, &val8);
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return val8;
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case PCI_SIZE_16:
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pci_read_config_word(dev, offset, &val16);
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return val16;
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case PCI_SIZE_32:
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default:
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pci_read_config_dword(dev, offset, &val32);
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return val32;
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}
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}
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static void pci_show_regs(pci_dev_t dev, struct pci_reg_info *regs)
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{
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for (; regs->name; regs++) {
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printf(" %s =%*s%#.*lx\n", regs->name,
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(int)(28 - strlen(regs->name)), "",
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pci_field_width(regs->size),
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pci_read_config(dev, regs->offset, regs->size));
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}
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}
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#endif
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#ifdef CONFIG_DM_PCI
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int pci_bar_show(struct udevice *dev)
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{
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u8 header_type;
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int bar_cnt, bar_id, mem_type;
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bool is_64, is_io;
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u32 base_low, base_high;
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u32 size_low, size_high;
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u64 base, size;
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u32 reg_addr;
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int prefetchable;
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dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
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if (header_type == PCI_HEADER_TYPE_CARDBUS) {
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printf("CardBus doesn't support BARs\n");
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return -ENOSYS;
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}
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bar_cnt = (header_type == PCI_HEADER_TYPE_NORMAL) ? 6 : 2;
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printf("ID Base Size Width Type\n");
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printf("----------------------------------------------------------\n");
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bar_id = 0;
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reg_addr = PCI_BASE_ADDRESS_0;
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while (bar_cnt) {
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dm_pci_read_config32(dev, reg_addr, &base_low);
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dm_pci_write_config32(dev, reg_addr, 0xffffffff);
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dm_pci_read_config32(dev, reg_addr, &size_low);
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dm_pci_write_config32(dev, reg_addr, base_low);
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reg_addr += 4;
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base = base_low & ~0xf;
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size = size_low & ~0xf;
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base_high = 0x0;
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size_high = 0xffffffff;
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is_64 = 0;
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prefetchable = base_low & PCI_BASE_ADDRESS_MEM_PREFETCH;
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is_io = base_low & PCI_BASE_ADDRESS_SPACE_IO;
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mem_type = base_low & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
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if (mem_type == PCI_BASE_ADDRESS_MEM_TYPE_64) {
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dm_pci_read_config32(dev, reg_addr, &base_high);
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dm_pci_write_config32(dev, reg_addr, 0xffffffff);
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dm_pci_read_config32(dev, reg_addr, &size_high);
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dm_pci_write_config32(dev, reg_addr, base_high);
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bar_cnt--;
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reg_addr += 4;
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is_64 = 1;
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}
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base = base | ((u64)base_high << 32);
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size = size | ((u64)size_high << 32);
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if ((!is_64 && size_low) || (is_64 && size)) {
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size = ~size + 1;
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printf(" %d %#018llx %#018llx %d %s %s\n",
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bar_id, (unsigned long long)base,
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(unsigned long long)size, is_64 ? 64 : 32,
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is_io ? "I/O" : "MEM",
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prefetchable ? "Prefetchable" : "");
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}
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bar_id++;
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bar_cnt--;
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}
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return 0;
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}
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#endif
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static struct pci_reg_info regs_start[] = {
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{ "vendor ID", PCI_SIZE_16, PCI_VENDOR_ID },
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{ "device ID", PCI_SIZE_16, PCI_DEVICE_ID },
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{ "command register ID", PCI_SIZE_16, PCI_COMMAND },
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{ "status register", PCI_SIZE_16, PCI_STATUS },
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{ "revision ID", PCI_SIZE_8, PCI_REVISION_ID },
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{},
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};
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static struct pci_reg_info regs_rest[] = {
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{ "sub class code", PCI_SIZE_8, PCI_CLASS_SUB_CODE },
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{ "programming interface", PCI_SIZE_8, PCI_CLASS_PROG },
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{ "cache line", PCI_SIZE_8, PCI_CACHE_LINE_SIZE },
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{ "latency time", PCI_SIZE_8, PCI_LATENCY_TIMER },
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{ "header type", PCI_SIZE_8, PCI_HEADER_TYPE },
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{ "BIST", PCI_SIZE_8, PCI_BIST },
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{ "base address 0", PCI_SIZE_32, PCI_BASE_ADDRESS_0 },
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{},
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};
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static struct pci_reg_info regs_normal[] = {
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{ "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
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{ "base address 2", PCI_SIZE_32, PCI_BASE_ADDRESS_2 },
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{ "base address 3", PCI_SIZE_32, PCI_BASE_ADDRESS_3 },
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{ "base address 4", PCI_SIZE_32, PCI_BASE_ADDRESS_4 },
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{ "base address 5", PCI_SIZE_32, PCI_BASE_ADDRESS_5 },
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{ "cardBus CIS pointer", PCI_SIZE_32, PCI_CARDBUS_CIS },
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{ "sub system vendor ID", PCI_SIZE_16, PCI_SUBSYSTEM_VENDOR_ID },
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{ "sub system ID", PCI_SIZE_16, PCI_SUBSYSTEM_ID },
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{ "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS },
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{ "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
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{ "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
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{ "min Grant", PCI_SIZE_8, PCI_MIN_GNT },
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{ "max Latency", PCI_SIZE_8, PCI_MAX_LAT },
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{},
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};
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static struct pci_reg_info regs_bridge[] = {
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{ "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
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{ "primary bus number", PCI_SIZE_8, PCI_PRIMARY_BUS },
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{ "secondary bus number", PCI_SIZE_8, PCI_SECONDARY_BUS },
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{ "subordinate bus number", PCI_SIZE_8, PCI_SUBORDINATE_BUS },
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{ "secondary latency timer", PCI_SIZE_8, PCI_SEC_LATENCY_TIMER },
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{ "IO base", PCI_SIZE_8, PCI_IO_BASE },
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{ "IO limit", PCI_SIZE_8, PCI_IO_LIMIT },
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{ "secondary status", PCI_SIZE_16, PCI_SEC_STATUS },
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{ "memory base", PCI_SIZE_16, PCI_MEMORY_BASE },
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{ "memory limit", PCI_SIZE_16, PCI_MEMORY_LIMIT },
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{ "prefetch memory base", PCI_SIZE_16, PCI_PREF_MEMORY_BASE },
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{ "prefetch memory limit", PCI_SIZE_16, PCI_PREF_MEMORY_LIMIT },
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{ "prefetch memory base upper", PCI_SIZE_32, PCI_PREF_BASE_UPPER32 },
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{ "prefetch memory limit upper", PCI_SIZE_32, PCI_PREF_LIMIT_UPPER32 },
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{ "IO base upper 16 bits", PCI_SIZE_16, PCI_IO_BASE_UPPER16 },
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{ "IO limit upper 16 bits", PCI_SIZE_16, PCI_IO_LIMIT_UPPER16 },
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{ "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS1 },
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{ "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
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{ "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
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{ "bridge control", PCI_SIZE_16, PCI_BRIDGE_CONTROL },
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{},
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};
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static struct pci_reg_info regs_cardbus[] = {
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{ "capabilities", PCI_SIZE_8, PCI_CB_CAPABILITY_LIST },
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{ "secondary status", PCI_SIZE_16, PCI_CB_SEC_STATUS },
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{ "primary bus number", PCI_SIZE_8, PCI_CB_PRIMARY_BUS },
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{ "CardBus number", PCI_SIZE_8, PCI_CB_CARD_BUS },
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{ "subordinate bus number", PCI_SIZE_8, PCI_CB_SUBORDINATE_BUS },
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{ "CardBus latency timer", PCI_SIZE_8, PCI_CB_LATENCY_TIMER },
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{ "CardBus memory base 0", PCI_SIZE_32, PCI_CB_MEMORY_BASE_0 },
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{ "CardBus memory limit 0", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_0 },
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{ "CardBus memory base 1", PCI_SIZE_32, PCI_CB_MEMORY_BASE_1 },
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{ "CardBus memory limit 1", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_1 },
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{ "CardBus IO base 0", PCI_SIZE_16, PCI_CB_IO_BASE_0 },
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{ "CardBus IO base high 0", PCI_SIZE_16, PCI_CB_IO_BASE_0_HI },
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{ "CardBus IO limit 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0 },
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{ "CardBus IO limit high 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0_HI },
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{ "CardBus IO base 1", PCI_SIZE_16, PCI_CB_IO_BASE_1 },
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{ "CardBus IO base high 1", PCI_SIZE_16, PCI_CB_IO_BASE_1_HI },
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{ "CardBus IO limit 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1 },
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{ "CardBus IO limit high 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1_HI },
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{ "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
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{ "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
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{ "bridge control", PCI_SIZE_16, PCI_CB_BRIDGE_CONTROL },
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{ "subvendor ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_VENDOR_ID },
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{ "subdevice ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_ID },
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{ "PC Card 16bit base address", PCI_SIZE_32, PCI_CB_LEGACY_MODE_BASE },
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{},
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};
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/**
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* pci_header_show() - Show the header of the specified PCI device.
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*
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* @dev: Bus+Device+Function number
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*/
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#ifdef CONFIG_DM_PCI
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void pci_header_show(struct udevice *dev)
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#else
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void pci_header_show(pci_dev_t dev)
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#endif
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{
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#ifdef CONFIG_DM_PCI
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unsigned long class, header_type;
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dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
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dm_pci_read_config(dev, PCI_HEADER_TYPE, &header_type, PCI_SIZE_8);
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#else
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u8 class, header_type;
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pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
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pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
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#endif
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pci_show_regs(dev, regs_start);
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printf(" class code = 0x%.2x (%s)\n", (int)class,
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pci_class_str(class));
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pci_show_regs(dev, regs_rest);
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switch (header_type & 0x03) {
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case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
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pci_show_regs(dev, regs_normal);
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break;
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case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
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pci_show_regs(dev, regs_bridge);
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break;
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case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
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pci_show_regs(dev, regs_cardbus);
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break;
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default:
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printf("unknown header\n");
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break;
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}
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}
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void pciinfo_header(int busnum, bool short_listing)
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{
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printf("Scanning PCI devices on bus %d\n", busnum);
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if (short_listing) {
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printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
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printf("_____________________________________________________________\n");
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}
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}
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#ifdef CONFIG_DM_PCI
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/**
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* pci_header_show_brief() - Show the short-form PCI device header
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*
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* Reads and prints the header of the specified PCI device in short form.
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*
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* @dev: PCI device to show
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*/
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static void pci_header_show_brief(struct udevice *dev)
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{
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ulong vendor, device;
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ulong class, subclass;
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dm_pci_read_config(dev, PCI_VENDOR_ID, &vendor, PCI_SIZE_16);
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dm_pci_read_config(dev, PCI_DEVICE_ID, &device, PCI_SIZE_16);
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dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
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dm_pci_read_config(dev, PCI_CLASS_SUB_CODE, &subclass, PCI_SIZE_8);
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printf("0x%.4lx 0x%.4lx %-23s 0x%.2lx\n",
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vendor, device,
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pci_class_str(class), subclass);
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}
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static void pciinfo(struct udevice *bus, bool short_listing)
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{
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struct udevice *dev;
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pciinfo_header(bus->seq, short_listing);
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for (device_find_first_child(bus, &dev);
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dev;
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device_find_next_child(&dev)) {
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struct pci_child_platdata *pplat;
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pplat = dev_get_parent_platdata(dev);
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if (short_listing) {
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printf("%02x.%02x.%02x ", bus->seq,
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PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
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pci_header_show_brief(dev);
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} else {
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printf("\nFound PCI device %02x.%02x.%02x:\n", bus->seq,
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PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
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pci_header_show(dev);
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}
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}
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}
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#else
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/**
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* pci_header_show_brief() - Show the short-form PCI device header
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*
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* Reads and prints the header of the specified PCI device in short form.
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*
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* @dev: Bus+Device+Function number
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*/
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void pci_header_show_brief(pci_dev_t dev)
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{
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u16 vendor, device;
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u8 class, subclass;
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pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
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pci_read_config_word(dev, PCI_DEVICE_ID, &device);
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pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
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pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);
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printf("0x%.4x 0x%.4x %-23s 0x%.2x\n",
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vendor, device,
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pci_class_str(class), subclass);
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}
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/**
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* pciinfo() - Show a list of devices on the PCI bus
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*
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* Show information about devices on PCI bus. Depending on @short_pci_listing
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* the output will be more or less exhaustive.
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*
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* @bus_num: The number of the bus to be scanned
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* @short_pci_listing: true to use short form, showing only a brief header
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* for each device
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*/
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void pciinfo(int bus_num, int short_pci_listing)
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{
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struct pci_controller *hose = pci_bus_to_hose(bus_num);
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int device;
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int function;
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unsigned char header_type;
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unsigned short vendor_id;
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pci_dev_t dev;
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int ret;
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if (!hose)
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return;
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pciinfo_header(bus_num, short_pci_listing);
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for (device = 0; device < PCI_MAX_PCI_DEVICES; device++) {
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header_type = 0;
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vendor_id = 0;
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for (function = 0; function < PCI_MAX_PCI_FUNCTIONS;
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function++) {
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/*
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* If this is not a multi-function device, we skip
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* the rest.
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*/
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if (function && !(header_type & 0x80))
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break;
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dev = PCI_BDF(bus_num, device, function);
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if (pci_skip_dev(hose, dev))
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continue;
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ret = pci_read_config_word(dev, PCI_VENDOR_ID,
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&vendor_id);
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if (ret)
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goto error;
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if ((vendor_id == 0xFFFF) || (vendor_id == 0x0000))
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continue;
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if (!function) {
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pci_read_config_byte(dev, PCI_HEADER_TYPE,
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&header_type);
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}
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if (short_pci_listing) {
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printf("%02x.%02x.%02x ", bus_num, device,
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function);
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pci_header_show_brief(dev);
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} else {
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printf("\nFound PCI device %02x.%02x.%02x:\n",
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bus_num, device, function);
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pci_header_show(dev);
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}
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}
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}
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return;
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error:
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printf("Cannot read bus configuration: %d\n", ret);
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}
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#endif
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/**
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* get_pci_dev() - Convert the "bus.device.function" identifier into a number
|
|
*
|
|
* @name: Device string in the form "bus.device.function" where each is in hex
|
|
* @return encoded pci_dev_t or -1 if the string was invalid
|
|
*/
|
|
static pci_dev_t get_pci_dev(char *name)
|
|
{
|
|
char cnum[12];
|
|
int len, i, iold, n;
|
|
int bdfs[3] = {0,0,0};
|
|
|
|
len = strlen(name);
|
|
if (len > 8)
|
|
return -1;
|
|
for (i = 0, iold = 0, n = 0; i < len; i++) {
|
|
if (name[i] == '.') {
|
|
memcpy(cnum, &name[iold], i - iold);
|
|
cnum[i - iold] = '\0';
|
|
bdfs[n++] = simple_strtoul(cnum, NULL, 16);
|
|
iold = i + 1;
|
|
}
|
|
}
|
|
strcpy(cnum, &name[iold]);
|
|
if (n == 0)
|
|
n = 1;
|
|
bdfs[n] = simple_strtoul(cnum, NULL, 16);
|
|
|
|
return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
|
|
}
|
|
|
|
#ifdef CONFIG_DM_PCI
|
|
static int pci_cfg_display(struct udevice *dev, ulong addr,
|
|
enum pci_size_t size, ulong length)
|
|
#else
|
|
static int pci_cfg_display(pci_dev_t bdf, ulong addr, enum pci_size_t size,
|
|
ulong length)
|
|
#endif
|
|
{
|
|
#define DISP_LINE_LEN 16
|
|
ulong i, nbytes, linebytes;
|
|
int byte_size;
|
|
int rc = 0;
|
|
|
|
byte_size = pci_byte_size(size);
|
|
if (length == 0)
|
|
length = 0x40 / byte_size; /* Standard PCI config space */
|
|
|
|
/* Print the lines.
|
|
* once, and all accesses are with the specified bus width.
|
|
*/
|
|
nbytes = length * byte_size;
|
|
do {
|
|
printf("%08lx:", addr);
|
|
linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
|
|
for (i = 0; i < linebytes; i += byte_size) {
|
|
unsigned long val;
|
|
|
|
#ifdef CONFIG_DM_PCI
|
|
dm_pci_read_config(dev, addr, &val, size);
|
|
#else
|
|
val = pci_read_config(bdf, addr, size);
|
|
#endif
|
|
printf(" %0*lx", pci_field_width(size), val);
|
|
addr += byte_size;
|
|
}
|
|
printf("\n");
|
|
nbytes -= linebytes;
|
|
if (ctrlc()) {
|
|
rc = 1;
|
|
break;
|
|
}
|
|
} while (nbytes > 0);
|
|
|
|
return (rc);
|
|
}
|
|
|
|
#ifndef CONFIG_DM_PCI
|
|
static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
|
|
{
|
|
if (size == 4) {
|
|
pci_write_config_dword(bdf, addr, value);
|
|
}
|
|
else if (size == 2) {
|
|
ushort val = value & 0xffff;
|
|
pci_write_config_word(bdf, addr, val);
|
|
}
|
|
else {
|
|
u_char val = value & 0xff;
|
|
pci_write_config_byte(bdf, addr, val);
|
|
}
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_DM_PCI
|
|
static int pci_cfg_modify(struct udevice *dev, ulong addr, ulong size,
|
|
ulong value, int incrflag)
|
|
#else
|
|
static int pci_cfg_modify(pci_dev_t bdf, ulong addr, ulong size, ulong value,
|
|
int incrflag)
|
|
#endif
|
|
{
|
|
ulong i;
|
|
int nbytes;
|
|
ulong val;
|
|
|
|
/* Print the address, followed by value. Then accept input for
|
|
* the next value. A non-converted value exits.
|
|
*/
|
|
do {
|
|
printf("%08lx:", addr);
|
|
#ifdef CONFIG_DM_PCI
|
|
dm_pci_read_config(dev, addr, &val, size);
|
|
#else
|
|
val = pci_read_config(bdf, addr, size);
|
|
#endif
|
|
printf(" %0*lx", pci_field_width(size), val);
|
|
|
|
nbytes = cli_readline(" ? ");
|
|
if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
|
|
/* <CR> pressed as only input, don't modify current
|
|
* location and move to next. "-" pressed will go back.
|
|
*/
|
|
if (incrflag)
|
|
addr += nbytes ? -size : size;
|
|
nbytes = 1;
|
|
/* good enough to not time out */
|
|
bootretry_reset_cmd_timeout();
|
|
}
|
|
#ifdef CONFIG_BOOT_RETRY_TIME
|
|
else if (nbytes == -2) {
|
|
break; /* timed out, exit the command */
|
|
}
|
|
#endif
|
|
else {
|
|
char *endp;
|
|
i = simple_strtoul(console_buffer, &endp, 16);
|
|
nbytes = endp - console_buffer;
|
|
if (nbytes) {
|
|
/* good enough to not time out
|
|
*/
|
|
bootretry_reset_cmd_timeout();
|
|
#ifdef CONFIG_DM_PCI
|
|
dm_pci_write_config(dev, addr, i, size);
|
|
#else
|
|
pci_cfg_write(bdf, addr, size, i);
|
|
#endif
|
|
if (incrflag)
|
|
addr += size;
|
|
}
|
|
}
|
|
} while (nbytes);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_DM_PCI
|
|
static const struct pci_flag_info {
|
|
uint flag;
|
|
const char *name;
|
|
} pci_flag_info[] = {
|
|
{ PCI_REGION_IO, "io" },
|
|
{ PCI_REGION_PREFETCH, "prefetch" },
|
|
{ PCI_REGION_SYS_MEMORY, "sysmem" },
|
|
{ PCI_REGION_RO, "readonly" },
|
|
{ PCI_REGION_IO, "io" },
|
|
};
|
|
|
|
static void pci_show_regions(struct udevice *bus)
|
|
{
|
|
struct pci_controller *hose = dev_get_uclass_priv(bus);
|
|
const struct pci_region *reg;
|
|
int i, j;
|
|
|
|
if (!hose) {
|
|
printf("Bus '%s' is not a PCI controller\n", bus->name);
|
|
return;
|
|
}
|
|
|
|
printf("# %-18s %-18s %-18s %s\n", "Bus start", "Phys start", "Size",
|
|
"Flags");
|
|
for (i = 0, reg = hose->regions; i < hose->region_count; i++, reg++) {
|
|
printf("%d %#018llx %#018llx %#018llx ", i,
|
|
(unsigned long long)reg->bus_start,
|
|
(unsigned long long)reg->phys_start,
|
|
(unsigned long long)reg->size);
|
|
if (!(reg->flags & PCI_REGION_TYPE))
|
|
printf("mem ");
|
|
for (j = 0; j < ARRAY_SIZE(pci_flag_info); j++) {
|
|
if (reg->flags & pci_flag_info[j].flag)
|
|
printf("%s ", pci_flag_info[j].name);
|
|
}
|
|
printf("\n");
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/* PCI Configuration Space access commands
|
|
*
|
|
* Syntax:
|
|
* pci display[.b, .w, .l] bus.device.function} [addr] [len]
|
|
* pci next[.b, .w, .l] bus.device.function [addr]
|
|
* pci modify[.b, .w, .l] bus.device.function [addr]
|
|
* pci write[.b, .w, .l] bus.device.function addr value
|
|
*/
|
|
static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
|
{
|
|
ulong addr = 0, value = 0, cmd_size = 0;
|
|
enum pci_size_t size = PCI_SIZE_32;
|
|
#ifdef CONFIG_DM_PCI
|
|
struct udevice *dev, *bus;
|
|
#else
|
|
pci_dev_t dev;
|
|
#endif
|
|
int busnum = 0;
|
|
pci_dev_t bdf = 0;
|
|
char cmd = 's';
|
|
int ret = 0;
|
|
|
|
if (argc > 1)
|
|
cmd = argv[1][0];
|
|
|
|
switch (cmd) {
|
|
case 'd': /* display */
|
|
case 'n': /* next */
|
|
case 'm': /* modify */
|
|
case 'w': /* write */
|
|
/* Check for a size specification. */
|
|
cmd_size = cmd_get_data_size(argv[1], 4);
|
|
size = (cmd_size == 4) ? PCI_SIZE_32 : cmd_size - 1;
|
|
if (argc > 3)
|
|
addr = simple_strtoul(argv[3], NULL, 16);
|
|
if (argc > 4)
|
|
value = simple_strtoul(argv[4], NULL, 16);
|
|
case 'h': /* header */
|
|
#ifdef CONFIG_DM_PCI
|
|
case 'b': /* bars */
|
|
#endif
|
|
if (argc < 3)
|
|
goto usage;
|
|
if ((bdf = get_pci_dev(argv[2])) == -1)
|
|
return 1;
|
|
break;
|
|
#if defined(CONFIG_DM_PCI)
|
|
case 'e':
|
|
pci_init();
|
|
return 0;
|
|
#endif
|
|
case 'r': /* no break */
|
|
default: /* scan bus */
|
|
value = 1; /* short listing */
|
|
if (argc > 1) {
|
|
if (cmd != 'r' && argv[argc-1][0] == 'l') {
|
|
value = 0;
|
|
argc--;
|
|
}
|
|
if (argc > 1)
|
|
busnum = simple_strtoul(argv[1], NULL, 16);
|
|
}
|
|
#ifdef CONFIG_DM_PCI
|
|
ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus);
|
|
if (ret) {
|
|
printf("No such bus\n");
|
|
return CMD_RET_FAILURE;
|
|
}
|
|
if (cmd == 'r')
|
|
pci_show_regions(bus);
|
|
else
|
|
pciinfo(bus, value);
|
|
#else
|
|
pciinfo(busnum, value);
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_DM_PCI
|
|
ret = dm_pci_bus_find_bdf(bdf, &dev);
|
|
if (ret) {
|
|
printf("No such device\n");
|
|
return CMD_RET_FAILURE;
|
|
}
|
|
#else
|
|
dev = bdf;
|
|
#endif
|
|
|
|
switch (argv[1][0]) {
|
|
case 'h': /* header */
|
|
pci_header_show(dev);
|
|
break;
|
|
case 'd': /* display */
|
|
return pci_cfg_display(dev, addr, size, value);
|
|
case 'n': /* next */
|
|
if (argc < 4)
|
|
goto usage;
|
|
ret = pci_cfg_modify(dev, addr, size, value, 0);
|
|
break;
|
|
case 'm': /* modify */
|
|
if (argc < 4)
|
|
goto usage;
|
|
ret = pci_cfg_modify(dev, addr, size, value, 1);
|
|
break;
|
|
case 'w': /* write */
|
|
if (argc < 5)
|
|
goto usage;
|
|
#ifdef CONFIG_DM_PCI
|
|
ret = dm_pci_write_config(dev, addr, value, size);
|
|
#else
|
|
ret = pci_cfg_write(dev, addr, size, value);
|
|
#endif
|
|
break;
|
|
#ifdef CONFIG_DM_PCI
|
|
|
|
case 'b': /* bars */
|
|
return pci_bar_show(dev);
|
|
#endif
|
|
default:
|
|
ret = CMD_RET_USAGE;
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
usage:
|
|
return CMD_RET_USAGE;
|
|
}
|
|
|
|
/***************************************************/
|
|
|
|
#ifdef CONFIG_SYS_LONGHELP
|
|
static char pci_help_text[] =
|
|
"[bus] [long]\n"
|
|
" - short or long list of PCI devices on bus 'bus'\n"
|
|
#if defined(CONFIG_DM_PCI)
|
|
"pci enum\n"
|
|
" - Enumerate PCI buses\n"
|
|
#endif
|
|
"pci header b.d.f\n"
|
|
" - show header of PCI device 'bus.device.function'\n"
|
|
#ifdef CONFIG_DM_PCI
|
|
"pci bar b.d.f\n"
|
|
" - show BARs base and size for device b.d.f'\n"
|
|
"pci regions\n"
|
|
" - show PCI regions\n"
|
|
#endif
|
|
"pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
|
|
" - display PCI configuration space (CFG)\n"
|
|
"pci next[.b, .w, .l] b.d.f address\n"
|
|
" - modify, read and keep CFG address\n"
|
|
"pci modify[.b, .w, .l] b.d.f address\n"
|
|
" - modify, auto increment CFG address\n"
|
|
"pci write[.b, .w, .l] b.d.f address value\n"
|
|
" - write to CFG address";
|
|
#endif
|
|
|
|
U_BOOT_CMD(
|
|
pci, 5, 1, do_pci,
|
|
"list and access PCI Configuration Space", pci_help_text
|
|
);
|