mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-21 02:33:07 +00:00
3c1057c548
Use the device sequence number in boot_instance variable
and no more the SDMMC instance provided by ROM code/TF-A.
After this patch we don't need to define the mmc alias in
device tree, for example:
mmc0 = &sdmmc1;
mmc1 = &sdmmc2;
mmc2 = &sdmmc3;
to have a correct mapping between the ROM code boot device =
"${boot_device}${boot_instance}" and the MMC device in U-Boot.
With this patch the 'mmc0' device (used in mmc commands) is
always used when only one instance sdmmc is activated in device
tree, even if it is only the sdmmc2 or sdmmc3.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
145 lines
3.8 KiB
C
145 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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#ifndef _MACH_STM32_H_
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#define _MACH_STM32_H_
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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#endif
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/*
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* Peripheral memory map
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* only address used before device tree parsing
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*/
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#define STM32_RCC_BASE 0x50000000
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#define STM32_PWR_BASE 0x50001000
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#define STM32_DBGMCU_BASE 0x50081000
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#define STM32_FMC2_BASE 0x58002000
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#define STM32_TZC_BASE 0x5C006000
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#define STM32_ETZPC_BASE 0x5C007000
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#define STM32_STGEN_BASE 0x5C008000
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#define STM32_TAMP_BASE 0x5C00A000
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#define STM32_USART1_BASE 0x5C000000
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#define STM32_USART2_BASE 0x4000E000
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#define STM32_USART3_BASE 0x4000F000
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#define STM32_UART4_BASE 0x40010000
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#define STM32_UART5_BASE 0x40011000
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#define STM32_USART6_BASE 0x44003000
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#define STM32_UART7_BASE 0x40018000
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#define STM32_UART8_BASE 0x40019000
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#define STM32_SDMMC1_BASE 0x58005000
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#define STM32_SDMMC2_BASE 0x58007000
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#define STM32_SDMMC3_BASE 0x48004000
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#define STM32_SYSRAM_BASE 0x2FFC0000
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#define STM32_SYSRAM_SIZE SZ_256K
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#define STM32_DDR_BASE 0xC0000000
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#define STM32_DDR_SIZE SZ_1G
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#ifndef __ASSEMBLY__
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/* enumerated used to identify the SYSCON driver instance */
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enum {
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STM32MP_SYSCON_UNKNOWN,
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STM32MP_SYSCON_SYSCFG,
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};
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/*
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* enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT
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* - boot device = bit 8:4
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* - boot instance = bit 3:0
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*/
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#define BOOT_TYPE_MASK 0xF0
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#define BOOT_TYPE_SHIFT 4
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#define BOOT_INSTANCE_MASK 0x0F
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#define BOOT_INSTANCE_SHIFT 0
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enum boot_device {
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BOOT_FLASH_SD = 0x10,
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BOOT_FLASH_SD_1 = 0x11,
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BOOT_FLASH_SD_2 = 0x12,
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BOOT_FLASH_SD_3 = 0x13,
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BOOT_FLASH_EMMC = 0x20,
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BOOT_FLASH_EMMC_1 = 0x21,
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BOOT_FLASH_EMMC_2 = 0x22,
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BOOT_FLASH_EMMC_3 = 0x23,
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BOOT_FLASH_NAND = 0x30,
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BOOT_FLASH_NAND_FMC = 0x31,
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BOOT_FLASH_NOR = 0x40,
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BOOT_FLASH_NOR_QSPI = 0x41,
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BOOT_SERIAL_UART = 0x50,
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BOOT_SERIAL_UART_1 = 0x51,
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BOOT_SERIAL_UART_2 = 0x52,
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BOOT_SERIAL_UART_3 = 0x53,
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BOOT_SERIAL_UART_4 = 0x54,
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BOOT_SERIAL_UART_5 = 0x55,
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BOOT_SERIAL_UART_6 = 0x56,
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BOOT_SERIAL_UART_7 = 0x57,
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BOOT_SERIAL_UART_8 = 0x58,
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BOOT_SERIAL_USB = 0x60,
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BOOT_SERIAL_USB_OTG = 0x62,
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BOOT_FLASH_SPINAND = 0x70,
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BOOT_FLASH_SPINAND_1 = 0x71,
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};
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/* TAMP registers */
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#define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x)
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#define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4)
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#define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5)
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#define TAMP_COPRO_RSC_TBL_ADDRESS TAMP_BACKUP_REGISTER(17)
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#define TAMP_COPRO_STATE TAMP_BACKUP_REGISTER(18)
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#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(20)
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#define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(21)
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#define TAMP_COPRO_STATE_OFF 0
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#define TAMP_COPRO_STATE_INIT 1
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#define TAMP_COPRO_STATE_CRUN 2
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#define TAMP_COPRO_STATE_CSTOP 3
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#define TAMP_COPRO_STATE_STANDBY 4
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#define TAMP_COPRO_STATE_CRASH 5
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#define TAMP_BOOT_MODE_MASK GENMASK(15, 8)
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#define TAMP_BOOT_MODE_SHIFT 8
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#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4)
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#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0)
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#define TAMP_BOOT_FORCED_MASK GENMASK(7, 0)
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#define TAMP_BOOT_DEBUG_ON BIT(16)
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enum forced_boot_mode {
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BOOT_NORMAL = 0x00,
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BOOT_FASTBOOT = 0x01,
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BOOT_RECOVERY = 0x02,
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BOOT_STM32PROG = 0x03,
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BOOT_UMS_MMC0 = 0x10,
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BOOT_UMS_MMC1 = 0x11,
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BOOT_UMS_MMC2 = 0x12,
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};
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/* offset used for BSEC driver: misc_read and misc_write */
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#define STM32_BSEC_SHADOW_OFFSET 0x0
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#define STM32_BSEC_SHADOW(id) (STM32_BSEC_SHADOW_OFFSET + (id) * 4)
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#define STM32_BSEC_OTP_OFFSET 0x80000000
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#define STM32_BSEC_OTP(id) (STM32_BSEC_OTP_OFFSET + (id) * 4)
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#define STM32_BSEC_LOCK_OFFSET 0xC0000000
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#define STM32_BSEC_LOCK(id) (STM32_BSEC_LOCK_OFFSET + (id) * 4)
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/* BSEC OTP index */
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#define BSEC_OTP_RPN 1
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#define BSEC_OTP_SERIAL 13
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#define BSEC_OTP_PKG 16
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#define BSEC_OTP_MAC 57
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#define BSEC_OTP_BOARD 59
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#endif /* __ASSEMBLY__ */
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#endif /* _MACH_STM32_H_ */
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