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d3daba10f1
AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A) Adding LPDDR2 init sequence and register details for the same. Below is the brief description of LPDDR2 init sequence: -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register -> Wait till initialization is complete and the configure MR registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
80 lines
2.1 KiB
C
80 lines
2.1 KiB
C
/*
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* hardware_am43xx.h
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*
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* AM43xx hardware specific header
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*
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* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __AM43XX_HARDWARE_AM43XX_H
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#define __AM43XX_HARDWARE_AM43XX_H
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/* Module base addresses */
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/* UART Base Address */
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#define UART0_BASE 0x44E09000
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/* GPIO Base address */
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#define GPIO2_BASE 0x481AC000
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/* Watchdog Timer */
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#define WDT_BASE 0x44E35000
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/* Control Module Base Address */
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#define CTRL_BASE 0x44E10000
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#define CTRL_DEVICE_BASE 0x44E10600
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/* PRCM Base Address */
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#define PRCM_BASE 0x44DF0000
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#define CM_WKUP 0x44DF2800
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#define CM_PER 0x44DF8800
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#define CM_DPLL 0x44DF4200
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#define CM_RTC 0x44DF8500
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#define PRM_RSTCTRL (PRCM_BASE + 0x4000)
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#define PRM_RSTST (PRM_RSTCTRL + 4)
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/* VTP Base address */
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#define VTP0_CTRL_ADDR 0x44E10E0C
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#define VTP1_CTRL_ADDR 0x48140E10
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/* DDR Base address */
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#define DDR_PHY_CMD_ADDR 0x44E12000
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#define DDR_PHY_DATA_ADDR 0x44E120C8
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#define DDR_PHY_CMD_ADDR2 0x47C0C800
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#define DDR_PHY_DATA_ADDR2 0x47C0C8C8
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#define DDR_DATA_REGS_NR 2
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/* CPSW Config space */
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#define CPSW_MDIO_BASE 0x4A101000
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/* RTC base address */
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#define RTC_BASE 0x44E3E000
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/* USB Clock Control */
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#define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260)
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#define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268)
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#define USBOTGSSX_CLKCTRL_MODULE_EN (1 << 1)
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#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8)
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#define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8)
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#define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0)
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#define USBPHYOCPSCP_MODULE_EN (1 << 1)
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#define CM_DEVICE_INST 0x44df4100
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/* Control status register */
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#define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31)
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#define CTRL_CRYSTAL_FREQ_SRC_SHIFT 31
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#define CTRL_CRYSTAL_FREQ_SELECTION_MASK (0x3 << 29)
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#define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT 29
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#define CTRL_SYSBOOT_15_14_MASK (0x3 << 22)
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#define CTRL_SYSBOOT_15_14_SHIFT 22
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#define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT 0x0
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#define CTRL_CRYSTAL_FREQ_SRC_EFUSE 0x1
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#define NUM_CRYSTAL_FREQ 0x4
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#endif /* __AM43XX_HARDWARE_AM43XX_H */
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