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d054c2f8c6
DP501 only supports DP 1.1a. Limit settings for link bandwidth and lane count to values allowed by DP 1.1a. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
127 lines
3.7 KiB
C
127 lines
3.7 KiB
C
/*
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* (C) Copyright 2012
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* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* Parade Technologies Inc. DP501 DisplayPort DVI/HDMI Transmitter */
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#include <common.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <i2c.h>
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static void dp501_setbits(u8 addr, u8 reg, u8 mask)
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{
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u8 val;
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val = i2c_reg_read(addr, reg);
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setbits_8(&val, mask);
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i2c_reg_write(addr, reg, val);
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}
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static void dp501_clrbits(u8 addr, u8 reg, u8 mask)
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{
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u8 val;
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val = i2c_reg_read(addr, reg);
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clrbits_8(&val, mask);
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i2c_reg_write(addr, reg, val);
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}
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static int dp501_detect_cable_adapter(u8 addr)
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{
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u8 val = i2c_reg_read(addr, 0x00);
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return !(val & 0x04);
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}
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static void dp501_link_training(u8 addr)
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{
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u8 val;
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u8 link_bw;
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u8 max_lane_cnt;
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u8 lane_cnt;
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val = i2c_reg_read(addr, 0x51);
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if (val >= 0x0a)
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link_bw = 0x0a;
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else
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link_bw = 0x06;
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if (link_bw != val)
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printf("DP sink supports %d Mbps link rate, set to %d Mbps\n",
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val * 270, link_bw * 270);
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i2c_reg_write(addr, 0x5d, link_bw); /* set link_bw */
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val = i2c_reg_read(addr, 0x52);
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max_lane_cnt = val & 0x1f;
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if (max_lane_cnt >= 4)
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lane_cnt = 4;
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else
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lane_cnt = max_lane_cnt;
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if (lane_cnt != max_lane_cnt)
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printf("DP sink supports %d lanes, set to %d lanes\n",
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max_lane_cnt, lane_cnt);
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i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */
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val = i2c_reg_read(addr, 0x53);
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i2c_reg_write(addr, 0x5c, val); /* set downspread_ctl */
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i2c_reg_write(addr, 0x5f, 0x0d); /* start training */
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}
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void dp501_powerup(u8 addr)
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{
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dp501_clrbits(addr, 0x0a, 0x30); /* power on encoder */
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dp501_setbits(addr, 0x0a, 0x0e); /* block HDCP and MCCS on I2C bride*/
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i2c_reg_write(addr, 0x27, 0x30); /* Hardware auto detect DVO timing */
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dp501_setbits(addr, 0x72, 0x80); /* DPCD read enable */
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dp501_setbits(addr, 0x30, 0x20); /* RS polynomial select */
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i2c_reg_write(addr, 0x71, 0x20); /* Enable Aux burst write */
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dp501_setbits(addr, 0x78, 0x30); /* Disable HPD2 IRQ */
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dp501_clrbits(addr, 0x2f, 0x40); /* Link FIFO reset selection */
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dp501_clrbits(addr, 0x60, 0x20); /* Enable scrambling */
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#ifdef CONFIG_SYS_DP501_VCAPCTRL0
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i2c_reg_write(addr, 0x24, CONFIG_SYS_DP501_VCAPCTRL0);
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#else
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i2c_reg_write(addr, 0x24, 0xc0); /* SDR mode 0, ext. H/VSYNC */
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#endif
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#ifdef CONFIG_SYS_DP501_DIFFERENTIAL
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i2c_reg_write(addr + 2, 0x24, 0x10); /* clock input differential */
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i2c_reg_write(addr + 2, 0x25, 0x04);
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i2c_reg_write(addr + 2, 0x26, 0x10);
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#else
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i2c_reg_write(addr + 2, 0x24, 0x02); /* clock input single ended */
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#endif
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i2c_reg_write(addr + 2, 0x1a, 0x04); /* SPDIF input method TTL */
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i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */
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i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */
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i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */
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i2c_reg_write(addr, 0x2d, 0x00); /* configure N value */
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i2c_reg_write(addr, 0x2e, 0x0c); /* configure N value */
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i2c_reg_write(addr, 0x76, 0xff); /* clear all interrupt */
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dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */
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i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */
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i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */
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i2c_reg_write(addr, 0x87, 0x7f); /* set retry counter as 7
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retry interval 400us */
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if (dp501_detect_cable_adapter(addr)) {
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printf("DVI/HDMI cable adapter detected\n");
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i2c_reg_write(addr, 0x5e, 0x04); /* enable 4 channel */
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dp501_clrbits(addr, 0x00, 0x08); /* DVI/HDMI HDCP operation */
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} else {
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printf("no DVI/HDMI cable adapter detected\n");
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dp501_setbits(addr, 0x00, 0x08); /* for DP HDCP operation */
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dp501_link_training(addr);
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}
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}
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void dp501_powerdown(u8 addr)
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{
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dp501_setbits(addr, 0x0a, 0x30); /* power down encoder, standby mode */
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}
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