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3041e094e4
In some situations the GSC firmware where the EEPROM containing the model and DRAM configuration may not be ready by the time the SoC is ready to talk to it over I2C. Instead of a hard delay, poll the I2C lines to wait until they are released to avoid the I2C drivers 'Arbitation lost' error message. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
169 lines
3.8 KiB
Text
169 lines
3.8 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2022 Gateworks Corporation
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*/
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/dts-v1/;
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#include "imx8mn.dtsi"
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/ {
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model = "Gateworks Venice i.MX8MM board";
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compatible = "gw,imx8mn-venice", "fsl,imx8mn";
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chosen {
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stdout-path = &uart2;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x0 0x40000000 0 0x80000000>;
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};
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c1>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
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sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
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status = "okay";
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gsc: gsc@20 {
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compatible = "gw,gsc";
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reg = <0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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eeprom@51 {
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compatible = "atmel,24c02";
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reg = <0x51>;
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pagesize = <16>;
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};
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};
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&i2c2 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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eeprom@52 {
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compatible = "atmel,24c32";
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reg = <0x52>;
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pagesize = <32>;
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};
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};
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/* console */
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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/* eMMC */
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&usdhc3 {
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assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
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assigned-clock-rates = <400000000>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,ext-reset-output;
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status = "okay";
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};
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&iomuxc {
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
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MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
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>;
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};
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pinctrl_i2c1_gpio: i2c1grp-gpio-grp {
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fsl,pins = <
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MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
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MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
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MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
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MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
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>;
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};
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pinctrl_usdhc3: usdhc3grp {
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fsl,pins = <
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MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
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MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
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MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
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MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
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MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
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MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
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MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
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MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
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MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
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MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
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MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
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>;
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};
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pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
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fsl,pins = <
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MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
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MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
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MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
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MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
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MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
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MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
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MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
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MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
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MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
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MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
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MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
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>;
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};
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pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
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fsl,pins = <
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MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
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MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
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MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
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MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
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MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
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MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
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MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
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MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
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MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
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MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
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MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
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>;
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};
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pinctrl_wdog: wdoggrp {
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fsl,pins = <
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MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
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>;
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};
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};
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