mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 18:59:44 +00:00
f38f5f4bcf
This patch adds board support for the Toradex Apalis TK1 a computer on module which can be used on different carrier boards. The module consists of a Tegra TK1 SoC, a PMIC solution, 2 GB of DDR3L RAM, a bunch of level shifters, an eMMC, a TMP451 temperature sensor chip, an I210 gigabit Ethernet controller and a SGTL5000 audio codec. Furthermore, there is a Kinetis MK20DN512 companion micro controller for analogue, CAN and resistive touch functionality. For the sake of ease of use we do not distinguish between different carrier boards for now as the base module features are deemed sufficient enough for regular booting. The following functionality is working so far: - eMMC boot, environment storage and Toradex factory config block - Gigabit Ethernet - MMC/SD cards (both MMC1 as well as SD1 slot) - USB client/host (dual role OTG port as client e.g. for DFU/UMS or host, other two ports as host) Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
41 lines
1.4 KiB
C
41 lines
1.4 KiB
C
/*
|
|
* Copyright (c) 2012-2016 Toradex, Inc.
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
/* AS3722-PMIC-specific early init regs */
|
|
|
|
#define AS3722_I2C_ADDR 0x80
|
|
|
|
#define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */
|
|
#define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */
|
|
#define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */
|
|
#define AS3722_SDCONTROL_REG 0x4D
|
|
|
|
#define AS3722_LDO1VOLTAGE_REG 0x11 /* VDD_SDMMC1 */
|
|
#define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */
|
|
#define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC3 */
|
|
#define AS3722_LDCONTROL_REG 0x4E
|
|
|
|
#define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
|
|
#define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG)
|
|
|
|
#define AS3722_SD1VOLTAGE_DATA (0x3200 | AS3722_SD1VOLTAGE_REG)
|
|
#define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG)
|
|
|
|
#define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG)
|
|
#define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG)
|
|
|
|
#define AS3722_LDO1CONTROL_DATA (0x0200 | AS3722_LDCONTROL_REG)
|
|
#define AS3722_LDO1VOLTAGE_DATA (0x7F00 | AS3722_LDO1VOLTAGE_REG)
|
|
|
|
#define AS3722_LDO2CONTROL_DATA (0x0400 | AS3722_LDCONTROL_REG)
|
|
#define AS3722_LDO2VOLTAGE_DATA (0x1000 | AS3722_LDO2VOLTAGE_REG)
|
|
|
|
#define AS3722_LDO6CONTROL_DATA (0x4000 | AS3722_LDCONTROL_REG)
|
|
#define AS3722_LDO6VOLTAGE_DATA (0x3F00 | AS3722_LDO6VOLTAGE_REG)
|
|
|
|
#define I2C_SEND_2_BYTES 0x0A02
|
|
|
|
void pmic_enable_cpu_vdd(void);
|