mirror of
https://github.com/AsahiLinux/u-boot
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a4bc38da27
Lot of PCIe controllers are using ECAM addressing. So add common ECAM macros into U-Boot's pci.h header file which can be suitable for most PCI controller drivers. Replace custom ECAM address macros in every PCI controller driver by new ECAM macros from U-Boot's pci.h header file. Similar macros are defined also in Linux kernel. There is a small difference between Linux and these new U-Boot macros. U-Boot's PCIE_ECAM_OFFSET() takes device and function numbers in separate arguments. Linux's PCIE_ECAM_OFFSET() takes device and function numbers encoded in one argument. The reason is that U-Boot's PCI_DEVFN() macro is different than Linux's PCI_SLOT() macro. So having device and function numbers in separate arguments makes code more straightforward. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
196 lines
5.2 KiB
C
196 lines
5.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Phytium PCIE host driver
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*
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* Heavily based on drivers/pci/pcie_xilinx.c
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*
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* Copyright (C) 2019
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*/
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#include <common.h>
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#include <dm.h>
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#include <pci.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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/**
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* struct phytium_pcie - phytium PCIe controller state
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* @cfg_base: The base address of memory mapped configuration space
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*/
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struct phytium_pcie {
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void *cfg_base;
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};
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/*
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* phytium_pci_skip_dev()
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* @parent: Identifies the PCIe device to access
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*
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* Checks whether the parent of the PCIe device is bridge
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*
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* Return: true if it is bridge, else false.
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*/
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static int phytium_pci_skip_dev(pci_dev_t parent)
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{
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unsigned char pos, id;
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unsigned long addr = 0x40000000;
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unsigned short capreg;
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unsigned char port_type;
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addr += PCIE_ECAM_OFFSET(PCI_BUS(parent), PCI_DEV(parent), PCI_FUNC(parent), 0);
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pos = 0x34;
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while (1) {
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pos = readb(addr + pos);
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if (pos < 0x40)
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break;
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pos &= ~3;
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id = readb(addr + pos);
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if (id == 0xff)
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break;
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if (id == 0x10) {
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capreg = readw(addr + pos + 2);
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port_type = (capreg >> 4) & 0xf;
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if (port_type == 0x6 || port_type == 0x4)
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return 1;
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else
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return 0;
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}
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pos += 1;
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}
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return 0;
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}
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/**
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* pci_phytium_conf_address() - Calculate the address of a config access
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* @bus: Pointer to the PCI bus
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* @bdf: Identifies the PCIe device to access
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* @offset: The offset into the device's configuration space
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* @paddress: Pointer to the pointer to write the calculates address to
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*
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* Calculates the address that should be accessed to perform a PCIe
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* configuration space access for a given device identified by the PCIe
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* controller device @pcie and the bus, device & function numbers in @bdf. If
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* access to the device is not valid then the function will return an error
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* code. Otherwise the address to access will be written to the pointer pointed
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* to by @paddress.
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*/
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static int pci_phytium_conf_address(const struct udevice *bus, pci_dev_t bdf,
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uint offset, void **paddress)
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{
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struct phytium_pcie *pcie = dev_get_priv(bus);
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void *addr;
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pci_dev_t bdf_parent;
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unsigned int bus_no = PCI_BUS(bdf);
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unsigned int dev_no = PCI_DEV(bdf);
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bdf_parent = PCI_BDF((bus_no - 1), 0, 0);
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addr = pcie->cfg_base;
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addr += PCIE_ECAM_OFFSET(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), 0);
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if (bus_no > 0 && dev_no > 0) {
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if ((readb(addr + PCI_HEADER_TYPE) & 0x7f) !=
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PCI_HEADER_TYPE_BRIDGE)
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return -ENODEV;
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if (phytium_pci_skip_dev(bdf_parent))
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return -ENODEV;
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}
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addr += offset;
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*paddress = addr;
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return 0;
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}
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/**
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* pci_phytium_read_config() - Read from configuration space
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* @bus: Pointer to the PCI bus
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* @bdf: Identifies the PCIe device to access
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* @offset: The offset into the device's configuration space
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* @valuep: A pointer at which to store the read value
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* @size: Indicates the size of access to perform
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*
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* Read a value of size @size from offset @offset within the configuration
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* space of the device identified by the bus, device & function numbers in @bdf
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* on the PCI bus @bus.
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*/
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static int pci_phytium_read_config(const struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong *valuep,
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enum pci_size_t size)
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{
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return pci_generic_mmap_read_config(bus, pci_phytium_conf_address,
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bdf, offset, valuep, size);
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}
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/**
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* pci_phytium_write_config() - Write to configuration space
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* @bus: Pointer to the PCI bus
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* @bdf: Identifies the PCIe device to access
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* @offset: The offset into the device's configuration space
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* @value: The value to write
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* @size: Indicates the size of access to perform
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*
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* Write the value @value of size @size from offset @offset within the
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* configuration space of the device identified by the bus, device & function
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* numbers in @bdf on the PCI bus @bus.
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*/
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static int pci_phytium_write_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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return pci_generic_mmap_write_config(bus, pci_phytium_conf_address,
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bdf, offset, value, size);
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}
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/**
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* pci_phytium_of_to_plat() - Translate from DT to device state
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* @dev: A pointer to the device being operated on
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*
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* Translate relevant data from the device tree pertaining to device @dev into
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* state that the driver will later make use of. This state is stored in the
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* device's private data structure.
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*
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* Return: 0 on success, else -EINVAL
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*/
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static int pci_phytium_of_to_plat(struct udevice *dev)
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{
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struct phytium_pcie *pcie = dev_get_priv(dev);
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struct fdt_resource reg_res;
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DECLARE_GLOBAL_DATA_PTR;
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int err;
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err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg",
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0, ®_res);
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if (err < 0) {
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pr_err("\"reg\" resource not found\n");
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return err;
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}
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pcie->cfg_base = map_physmem(reg_res.start,
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fdt_resource_size(®_res),
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MAP_NOCACHE);
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return 0;
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}
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static const struct dm_pci_ops pci_phytium_ops = {
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.read_config = pci_phytium_read_config,
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.write_config = pci_phytium_write_config,
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};
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static const struct udevice_id pci_phytium_ids[] = {
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{ .compatible = "phytium,pcie-host-1.0" },
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{ }
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};
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U_BOOT_DRIVER(pci_phytium) = {
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.name = "pci_phytium",
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.id = UCLASS_PCI,
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.of_match = pci_phytium_ids,
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.ops = &pci_phytium_ops,
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.of_to_plat = pci_phytium_of_to_plat,
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.priv_auto = sizeof(struct phytium_pcie),
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};
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