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38254f45b0
This is an SPI driver for i.MX and MXC based SoCs from Freescale. So far only implemented and tested on i.MX31, can with a modified register layout and definitions be used for i.MX27, I think, MXC CPUs have similar SPI controllers too. Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
166 lines
4.2 KiB
C
166 lines
4.2 KiB
C
/*
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* Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <spi.h>
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#include <asm/io.h>
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#ifdef CONFIG_MX27
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/* i.MX27 has a completely wrong register layout and register definitions in the
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* datasheet, the correct one is in the Freescale's Linux driver */
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#error "i.MX27 CSPI not supported due to drastic differences in register definisions" \
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"See linux mxc_spi driver from Freescale for details."
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#else
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#define MXC_CSPIRXDATA 0x00
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#define MXC_CSPITXDATA 0x04
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#define MXC_CSPICTRL 0x08
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#define MXC_CSPIINT 0x0C
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#define MXC_CSPIDMA 0x10
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#define MXC_CSPISTAT 0x14
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#define MXC_CSPIPERIOD 0x18
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#define MXC_CSPITEST 0x1C
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#define MXC_CSPIRESET 0x00
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#define MXC_CSPICTRL_EN (1 << 0)
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#define MXC_CSPICTRL_MODE (1 << 1)
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#define MXC_CSPICTRL_XCH (1 << 2)
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#define MXC_CSPICTRL_SMC (1 << 3)
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#define MXC_CSPICTRL_POL (1 << 4)
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#define MXC_CSPICTRL_PHA (1 << 5)
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#define MXC_CSPICTRL_SSCTL (1 << 6)
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#define MXC_CSPICTRL_SSPOL (1 << 7)
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#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
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#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
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#define MXC_CSPIPERIOD_32KHZ (1 << 15)
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static unsigned long spi_bases[] = {
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0x43fa4000,
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0x50010000,
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0x53f84000,
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};
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static unsigned long spi_base;
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#endif
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spi_chipsel_type spi_chipsel[] = {
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(spi_chipsel_type)0,
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(spi_chipsel_type)1,
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(spi_chipsel_type)2,
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(spi_chipsel_type)3,
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};
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int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
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static inline u32 reg_read(unsigned long addr)
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{
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return *(volatile unsigned long*)addr;
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}
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static inline void reg_write(unsigned long addr, u32 val)
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{
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*(volatile unsigned long*)addr = val;
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}
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static u32 spi_xchg_single(u32 data, int bitlen)
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{
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unsigned int cfg_reg = reg_read(spi_base + MXC_CSPICTRL);
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if (MXC_CSPICTRL_BITCOUNT(bitlen - 1) != (cfg_reg & MXC_CSPICTRL_BITCOUNT(31))) {
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cfg_reg = (cfg_reg & ~MXC_CSPICTRL_BITCOUNT(31)) |
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MXC_CSPICTRL_BITCOUNT(bitlen - 1);
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reg_write(spi_base + MXC_CSPICTRL, cfg_reg);
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}
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reg_write(spi_base + MXC_CSPITXDATA, data);
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cfg_reg |= MXC_CSPICTRL_XCH;
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reg_write(spi_base + MXC_CSPICTRL, cfg_reg);
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while (reg_read(spi_base + MXC_CSPICTRL) & MXC_CSPICTRL_XCH)
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;
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return reg_read(spi_base + MXC_CSPIRXDATA);
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}
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int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din)
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{
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int n_blks = (bitlen + 31) / 32;
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u32 *out_l, *in_l;
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int i;
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if ((int)dout & 3 || (int)din & 3) {
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printf("Error: unaligned buffers in: %p, out: %p\n", din, dout);
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return 1;
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}
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if (!spi_base)
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spi_select(CONFIG_MXC_SPI_IFACE, (int)chipsel, SPI_MODE_2 | SPI_CS_HIGH);
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for (i = 0, in_l = (u32 *)din, out_l = (u32 *)dout;
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i < n_blks;
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i++, in_l++, out_l++, bitlen -= 32)
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*in_l = spi_xchg_single(*out_l, bitlen);
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return 0;
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}
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void spi_init(void)
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{
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}
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int spi_select(unsigned int bus, unsigned int dev, unsigned long mode)
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{
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unsigned int ctrl_reg;
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if (bus >= sizeof(spi_bases) / sizeof(spi_bases[0]) ||
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dev > 3)
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return 1;
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spi_base = spi_bases[bus];
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ctrl_reg = MXC_CSPICTRL_CHIPSELECT(dev) |
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MXC_CSPICTRL_BITCOUNT(31) |
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MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */
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MXC_CSPICTRL_EN |
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MXC_CSPICTRL_MODE;
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if (mode & SPI_CPHA)
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ctrl_reg |= MXC_CSPICTRL_PHA;
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if (!(mode & SPI_CPOL))
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ctrl_reg |= MXC_CSPICTRL_POL;
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if (mode & SPI_CS_HIGH)
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ctrl_reg |= MXC_CSPICTRL_SSPOL;
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reg_write(spi_base + MXC_CSPIRESET, 1);
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udelay(1);
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reg_write(spi_base + MXC_CSPICTRL, ctrl_reg);
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reg_write(spi_base + MXC_CSPIPERIOD,
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MXC_CSPIPERIOD_32KHZ);
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reg_write(spi_base + MXC_CSPIINT, 0);
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return 0;
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}
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