Siva Durga Prasad Paladugu fbf7fb0f9f fpga: zynqmp: Modify PL bitstream loading sequence ... This patch modifies PL bitstream loading sequence as per latest Xilfpga which supports all variants of bitstream images generated from vivado and from bootgen. With this new change in Xilfpga, uboot doesn't need to validate and swap bitstream as it will be taken care inside Xilfpga. ZynqMP PL driver now checks for supporting PMUFW version before skipping the validation and swap sequence as there can be old PMUFW which doesn't supports this feature. In this case, driver uses old way of PL bitstream loading sequence. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>		2018-09-26 10:15:00 +02:00
..
arc	arch: types.h: factor out fixed width typedefs to int-ll64.h	2018-09-10 20:48:16 -04:00
arm	fpga: zynqmp: Modify PL bitstream loading sequence	2018-09-26 10:15:00 +02:00
m68k	m68k: ColdFire mcf5441x, add eSDHC support	2018-09-16 00:01:13 +02:00
microblaze	arch: types.h: factor out fixed width typedefs to int-ll64.h	2018-09-10 20:48:16 -04:00
mips	mips: mt7628a.dtsi: Add SPI clock-frequency property	2018-09-23 14:27:51 +02:00
nds32	arch: types.h: factor out fixed width typedefs to int-ll64.h	2018-09-10 20:48:16 -04:00
nios2	.gitignore: move *.dtb and *.dtb.S patterns to the top-level .gitignore	2018-06-18 14:43:12 -04:00
powerpc	misc: Add MPC83xx serdes driver	2018-09-18 08:12:21 -06:00
riscv	arch: types.h: factor out fixed width typedefs to int-ll64.h	2018-09-10 20:48:16 -04:00
sandbox	test: Add tests for CPU uclass	2018-09-18 08:12:21 -06:00
sh	sh: tmu: Zap get_tbclk and timer_read_counter	2018-09-15 03:19:07 +02:00
x86	x86: cpu: add docstring to scu_ipc_command()	2018-09-17 17:35:53 +08:00
xtensa	arch: types.h: factor out fixed width typedefs to int-ll64.h	2018-09-10 20:48:16 -04:00
.gitignore
Kconfig	sandbox: Enable bitrev library build	2018-09-18 00:01:18 -06:00