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https://github.com/AsahiLinux/u-boot
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322c0da86a
Add support for 1024x768 60p resolution and set it up this resolution by default. This resolution is still able to use only one GT line. But for example 800x600 60p has some issues with settings. That's why extend this table by tested resolutions. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/957e1e85a05744326ec2606dadc1af6e69976f37.1684312924.git.michal.simek@amd.com
680 lines
22 KiB
C
680 lines
22 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2023, Advanced Micro Devices, Inc.
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*
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*/
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#ifndef _VIDEO_ZYNQMP_DPSUB_H
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#define _VIDEO_ZYNQMP_DPSUB_H
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enum video_mode {
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VIDC_VM_640x480_60_P = 0,
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VIDC_VM_1024x768_60_P = 1,
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};
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enum {
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LANE_COUNT_1 = 1,
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LANE_COUNT_2 = 2,
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};
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enum {
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LINK_RATE_162GBPS = 0x06,
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LINK_RATE_270GBPS = 0x0A,
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LINK_RATE_540GBPS = 0x14,
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};
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enum video_color_depth {
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VIDC_BPC_6 = 6,
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VIDC_BPC_8 = 8,
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VIDC_BPC_10 = 10,
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VIDC_BPC_12 = 12,
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VIDC_BPC_14 = 14,
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VIDC_BPC_16 = 16,
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VIDC_BPC_NUM_SUPPORTED = 6,
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VIDC_BPC_UNKNOWN
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};
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enum video_color_encoding {
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DP_CENC_RGB = 0,
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DP_CENC_YONLY,
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};
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enum dp_dma_channel_type {
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VIDEO_CHAN,
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GRAPHICS_CHAN,
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};
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enum dp_dma_channel_state {
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DPDMA_DISABLE,
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DPDMA_ENABLE,
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DPDMA_IDLE,
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DPDMA_PAUSE
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};
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enum link_training_states {
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TS_CLOCK_RECOVERY,
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TS_CHANNEL_EQUALIZATION,
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TS_ADJUST_LINK_RATE,
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TS_ADJUST_LANE_COUNT,
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TS_FAILURE,
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TS_SUCCESS
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};
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enum video_frame_rate {
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VIDC_FR_60HZ = 60,
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VIDC_FR_NUM_SUPPORTED = 2,
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VIDC_FR_UNKNOWN
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};
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enum av_buf_video_modes {
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INTERLEAVED,
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SEMIPLANAR
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};
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enum av_buf_video_format {
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RGBA8888 = 1,
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};
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enum av_buf_video_stream {
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AVBUF_VIDSTREAM1_LIVE,
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AVBUF_VIDSTREAM1_NONLIVE,
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AVBUF_VIDSTREAM1_TPG,
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AVBUF_VIDSTREAM1_NONE,
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};
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enum av_buf_gfx_stream {
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AVBUF_VIDSTREAM2_DISABLEGFX = 0x0,
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AVBUF_VIDSTREAM2_NONLIVE_GFX = 0x4,
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AVBUF_VIDSTREAM2_LIVE_GFX = 0x8,
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AVBUF_VIDSTREAM2_NONE = 0xC0,
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};
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/**
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* struct aux_transaction - Description of an AUX channel transaction
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* @cmd_code: Command code of the transaction
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* @num_bytes: The number of bytes in the transaction's payload data
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* @address: The DPCD address of the transaction
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* @data: Payload data of the AUX channel transaction
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*/
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struct aux_transaction {
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u16 cmd_code;
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u8 num_bytes;
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u32 address;
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u8 *data;
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};
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/**
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* struct link_config - Description of link configuration
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* @lane_count: Currently selected lane count for this link
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* @link_rate: Currently selected link rate for this link
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* @scrambler_en: Flag to determine whether the scrambler is
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* enabled for this link
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* @enhanced_framing_mode: Flag to determine whether enhanced framing
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* mode is active for this link
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* @max_lane_count: Maximum lane count for this link
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* @max_link_rate: Maximum link rate for this link
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* @support_enhanced_framing_mode: Flag to indicate whether the link supports
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* enhanced framing mode
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* @vs_level: Voltage swing for each lane
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* @pe_level: Pre-emphasis/cursor level for each lane
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* @pattern: The current pattern currently in use over the main link
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*/
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struct link_config {
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u8 lane_count;
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u8 link_rate;
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u8 scrambler_en;
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u8 enhanced_framing_mode;
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u8 max_lane_count;
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u8 max_link_rate;
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u8 support_enhanced_framing_mode;
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u8 support_downspread_control;
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u8 vs_level;
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u8 pe_level;
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u8 pattern;
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};
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struct video_timing {
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u16 h_active;
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u16 h_front_porch;
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u16 h_sync_width;
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u16 h_back_porch;
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u16 h_total;
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bool h_sync_polarity;
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u16 v_active;
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u16 f0_pv_front_porch;
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u16 f0_pv_sync_width;
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u16 f0_pv_back_porch;
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u16 f0_pv_total;
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u16 f1_v_front_porch;
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u16 f1_v_sync_width;
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u16 f1_v_back_porch;
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u16 f1_v_total;
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bool v_sync_polarity;
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};
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struct video_timing_mode {
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enum video_mode vid_mode;
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char name[21];
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enum video_frame_rate frame_rate;
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struct video_timing video_timing;
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};
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/*
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* struct main_stream_attributes - Main Stream Attributes (MSA)
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* @pixel_clock_hz: The pixel clock of the stream (in Hz)
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* @h_start: Horizontal blank start (in pixels)
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* @v_start: Vertical blank start (in lines).
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* @misc0: Miscellaneous stream attributes 0
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* @misc1: Miscellaneous stream attributes 1
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* @n_vid N value for the video stream
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* @user_pixel_width: The width of the user data input port.
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* @data_per_plane: Used to translate the number of pixels per
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* line to the native internal 16-bit datapath.
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* @avg_bytes_per_tu: Average number of bytes per transfer unit,
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* scaled up by a factor of 1000.
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* @transfer_unit_size: Size of the transfer unit in the
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* framing logic.
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* @init_wait: Number of initial wait cycles at the start
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* of a new line by the framing logic.
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* @bits_per_color: Number of bits per color component.
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* @component_format: The component format currently in
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* use by the video stream.
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* @dynamic_range: The dynamic range currently in use
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* by the video stream.
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* @y_cb_cr_colorimetry: The YCbCr colorimetry currently in
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* use by the video stream.
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* @synchronous_clock_mode: Synchronous clock mode is currently
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* in use by the video stream.
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*/
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struct main_stream_attributes {
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struct video_timing_mode vid_timing_mode;
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u32 pixel_clock_hz;
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u32 h_start;
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u32 v_start;
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u32 misc0;
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u32 misc1;
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u32 n_vid;
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u32 user_pixel_width;
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u32 data_per_lane;
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u32 avg_bytes_per_tu;
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u32 transfer_unit_size;
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u32 init_wait;
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u32 bits_per_color;
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u8 component_format;
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u8 dynamic_range;
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u8 y_cb_cr_colorimetry;
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u8 synchronous_clock_mode;
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};
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struct av_buf_vid_attribute {
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enum av_buf_video_format video_format;
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u8 value;
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enum av_buf_video_modes mode;
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u32 sf[3];
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u8 sampling_en;
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u8 is_rgb;
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u8 swap;
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u8 bpp;
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};
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struct av_buf_mode {
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enum av_buf_video_stream video_src;
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enum av_buf_gfx_stream gfx_src;
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u8 video_clk;
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};
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struct dp_dma_descriptor {
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u32 control;
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u32 dscr_id;
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u32 xfer_size;
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u32 line_size_stride;
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u32 lsb_timestamp;
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u32 msb_timestamp;
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u32 addr_ext;
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u32 next_desr;
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u32 src_addr;
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u32 addr_ext_23;
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u32 addr_ext_45;
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u32 src_addr2;
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u32 src_addr3;
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u32 src_addr4;
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u32 src_addr5;
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u32 crc;
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};
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struct dp_dma_channel {
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struct dp_dma_descriptor *cur;
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};
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struct dp_dma_frame_buffer {
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u64 address;
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u32 size;
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u32 stride;
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u32 line_size;
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};
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struct dp_dma_gfx_channel {
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struct dp_dma_channel channel;
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u8 trigger_status;
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u8 av_buf_en;
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struct dp_dma_frame_buffer *frame_buffer;
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};
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struct dp_dma {
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phys_addr_t base_addr;
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struct dp_dma_gfx_channel gfx;
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};
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/**
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* struct zynqmp_dpsub_priv - Private structure
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* @dev: Device uclass for video_ops
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*/
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struct zynqmp_dpsub_priv {
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phys_addr_t base_addr;
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u32 clock;
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struct av_buf_vid_attribute *non_live_graphics;
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struct av_buf_mode av_mode;
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struct dp_dma_frame_buffer frame_buffer;
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struct link_config link_config;
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struct main_stream_attributes msa_config;
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struct dp_dma *dp_dma;
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enum video_mode video_mode;
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enum video_color_depth bpc;
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enum video_color_encoding color_encode;
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u32 pix_clk;
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u8 dpcd_rx_caps[16];
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u8 lane_status_ajd_reqs[6];
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u8 sink_count;
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u8 use_max_lane_count;
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u8 use_max_link_rate;
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u8 lane_count;
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u8 link_rate;
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u8 use_max_cfg_caps;
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u8 en_sync_clk_mode;
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};
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/**************************** Variable Definitions ****************************/
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#define TRAINING_PATTERN_SET 0x000C
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#define TRAINING_PATTERN_SET_OFF 0x0
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#define SCRAMBLING_DISABLE 0x0014
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#define TRAINING_PATTERN_SET_TP1 0x1
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#define TRAINING_PATTERN_SET_TP2 0x2
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#define TRAINING_PATTERN_SET_TP3 0x3
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#define AVBUF_BUF_4BIT_SF 0x11111
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#define AVBUF_BUF_5BIT_SF 0x10842
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#define AVBUF_BUF_6BIT_SF 0x10410
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#define AVBUF_BUF_8BIT_SF 0x10101
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#define AVBUF_BUF_10BIT_SF 0x10040
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#define AVBUF_BUF_12BIT_SF 0x10000
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#define AVBUF_BUF_6BPC 0x000
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#define AVBUF_BUF_8BPC 0x001
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#define AVBUF_BUF_10BPC 0x010
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#define AVBUF_BUF_12BPC 0x011
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#define AVBUF_CHBUF3 0x0000B01C
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#define AVBUF_CHBUF3_BURST_LEN_SHIFT 2
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#define AVBUF_CHBUF3_FLUSH_MASK 0x00000002
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#define AVBUF_CHBUF0_EN_MASK 0x00000001
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#define AVBUF_BUF_OUTPUT_AUD_VID_SELECT 0x0000B070
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#define AVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM2_SEL_MASK 0x0000000C
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#define AVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM1_SEL_MASK 0x00000003
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#define AVBUF_BUF_OUTPUT_AUD_VID_SELECT 0x0000B070
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#define AVBUF_BUF_GRAPHICS_COMP0_SCALE_FACTOR 0x0000B200
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#define AVBUF_V_BLEND_LAYER1_CONTROL 0x0000A01C
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#define AVBUF_V_BLEND_IN2CSC_COEFF0 0x0000A080
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#define AVBUF_BUF_FORMAT 0x0000B000
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#define AVBUF_BUF_FORMAT_NL_VID_FORMAT_MASK 0x0000001F
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#define AVBUF_BUF_FORMAT_NL_GRAPHX_FORMAT_MASK 0x00000F00
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#define AVBUF_BUF_FORMAT_NL_GRAPHX_FORMAT_SHIFT 8
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#define AVBUF_V_BLEND_LAYER0_CONTROL_RGB_MODE_SHIFT 1
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#define AVBUF_V_BLEND_OUTPUT_VID_FORMAT_EN_DOWNSAMPLE_SHIFT 4
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#define AVBUF_V_BLEND_OUTPUT_VID_FORMAT 0x0000A014
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#define AVBUF_V_BLEND_RGB2YCBCR_COEFF0 0x0000A020
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#define AVBUF_V_BLEND_LUMA_OUTCSC_OFFSET 0x0000A074
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#define AVBUF_V_BLEND_LUMA_IN1CSC_OFFSET_POST_OFFSET_SHIFT 16
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#define AVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG_VALUE_SHIFT 1
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#define AVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG 0x0000A00C
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#define DP_MAIN_STREAM_MISC0_COMPONENT_FORMAT_SHIFT 1
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#define DP_MAIN_STREAM_MISC0_DYNAMIC_RANGE_SHIFT 3
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#define DP_MAIN_STREAM_MISC0_YCBCR_COLORIMETRY_SHIFT 4
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#define DP_MAIN_STREAM_MISC1_Y_ONLY_EN_MASK 0x00000080
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#define DP_MAIN_STREAM_MISC0_COMPONENT_FORMAT_YCBCR422 0x1
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#define AVBUF_PL_CLK 0x0
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#define AVBUF_PS_CLK 0x1
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#define AVBUF_BUF_AUD_VID_CLK_SOURCE_VID_TIMING_SRC_SHIFT 2
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#define AVBUF_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC_SHIFT 0
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#define AVBUF_BUF_AUD_VID_CLK_SOURCE_AUD_CLK_SRC_SHIFT 1
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#define AVBUF_BUF_AUD_VID_CLK_SOURCE 0x0000B120
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#define AVBUF_BUF_SRST_REG 0x0000B124
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#define AVBUF_BUF_SRST_REG_VID_RST_MASK 0x00000002
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#define AVBUF_CLK_FPD_BASEADDR 0xFD1A0000
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#define AVBUF_CLK_LPD_BASEADDR 0xFF5E0000
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#define AVBUF_LPD_CTRL_OFFSET 16
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#define AVBUF_FPD_CTRL_OFFSET 12
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#define AVBUF_EXTERNAL_DIVIDER 2
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#define AVBUF_VIDEO_REF_CTRL 0x00000070
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#define AVBUF_VIDEO_REF_CTRL_SRCSEL_MASK 0x00000007
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#define AVBUF_VPLL_SRC_SEL 0
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#define AVBUF_DPLL_SRC_SEL 2
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#define AVBUF_RPLL_TO_FPD_SRC_SEL 3
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#define AVBUF_INPUT_REF_CLK 3333333333
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#define AVBUF_PLL_OUT_FREQ 1450000000
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#define AVBUF_INPUT_FREQ_PRECISION 100
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#define AVBUF_PRECISION 16
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#define AVBUF_SHIFT_DECIMAL BIT(16)
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#define AVBUF_DECIMAL (AVBUF_SHIFT_DECIMAL - 1)
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#define AVBUF_ENABLE_BIT 1
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#define AVBUF_DISABLE_BIT 0
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#define AVBUF_PLL_CTRL_BYPASS_SHIFT 3
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#define AVBUF_PLL_CTRL_FBDIV_SHIFT 8
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#define AVBUF_PLL_CTRL_DIV2_SHIFT 16
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#define AVBUF_PLL_CTRL_PRE_SRC_SHIFT 20
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#define AVBUF_PLL_CTRL 0x00000020
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#define AVBUF_PLL_CFG_CP_SHIFT 5
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#define AVBUF_PLL_CFG_RES_SHIFT 0
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#define AVBUF_PLL_CFG_LFHF_SHIFT 10
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#define AVBUF_PLL_CFG_LOCK_DLY_SHIFT 25
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#define AVBUF_PLL_CFG_LOCK_CNT_SHIFT 13
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#define AVBUF_PLL_FRAC_CFG 0x00000028
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#define AVBUF_PLL_FRAC_CFG_ENABLED_SHIFT 31
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#define AVBUF_PLL_FRAC_CFG_DATA_SHIFT 0
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#define AVBUF_PLL_CTRL_RESET_MASK 0x00000001
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#define AVBUF_PLL_CTRL_RESET_SHIFT 0
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#define AVBUF_PLL_STATUS 0x00000044
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#define AVBUF_REG_OFFSET 4
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#define AVBUF_PLL_CTRL_BYPASS_MASK 0x00000008
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#define AVBUF_PLL_CTRL_BYPASS_SHIFT 3
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#define AVBUF_DOMAIN_SWITCH_CTRL 0x00000044
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#define AVBUF_DOMAIN_SWITCH_DIVISOR0_MASK 0x00003F00
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#define AVBUF_DOMAIN_SWITCH_DIVISOR0_SHIFT 8
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#define AVBUF_PLL_CFG 0x00000024
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#define AVBUF_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC_SHIFT 0
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#define AVBUF_VIDEO_REF_CTRL_CLKACT_MASK 0x01000000
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#define AVBUF_VIDEO_REF_CTRL_CLKACT_SHIFT 24
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#define AVBUF_VIDEO_REF_CTRL_DIVISOR1_MASK 0x003F0000
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#define AVBUF_VIDEO_REF_CTRL_DIVISOR1_SHIFT 16
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#define AVBUF_VIDEO_REF_CTRL_DIVISOR0_MASK 0x00003F00
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#define AVBUF_VIDEO_REF_CTRL_DIVISOR0_SHIFT 8
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#define AVBUF_VIDEO_REF_CTRL_CLKACT_MASK 0x01000000
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#define AVBUF_VIDEO_REF_CTRL_CLKACT_SHIFT 24
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#define DP_INTERRUPT_SIG_STATE 0x0130
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#define DP_INTR_STATUS 0x03A0
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#define DP_INTERRUPT_SIG_STATE_HPD_STATE_MASK 0x00000001
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#define DP_INTR_HPD_EVENT_MASK 0x00000002
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#define DP_INTR_HPD_PULSE_DETECTED_MASK 0x00000010
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#define DP_HPD_DURATION 0x0150
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#define DP_FORCE_SCRAMBLER_RESET 0x00C0
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#define DP_ENABLE_MAIN_STREAM 0x0084
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#define DP_IS_CONNECTED_MAX_TIMEOUT_COUNT 50
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#define DP_0_LINK_RATE 20
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#define DP_0_LANE_COUNT 1
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#define DP_ENHANCED_FRAME_EN 0x0008
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#define DP_LANE_COUNT_SET 0x0004
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#define DP_LINK_BW_SET_162GBPS 0x06
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#define DP_LINK_BW_SET_270GBPS 0x0A
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#define DP_LINK_BW_SET_540GBPS 0x14
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#define DP_LINK_BW_SET 0x0000
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#define DP_DOWNSPREAD_CTRL 0x0018
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#define DP_SCRAMBLING_DISABLE 0x0014
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#define DP_AUX_CMD_READ 0x9
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#define DP_AUX_CMD_WRITE 0x8
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#define DP_AUX_CMD_I2C_READ 0x1
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#define DP_AUX_CMD_I2C_READ_MOT 0x5
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#define DP_AUX_CMD_I2C_WRITE 0x0
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#define DP_AUX_CMD_I2C_WRITE_MOT 0x4
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#define DP_REPLY_STATUS_REPLY_IN_PROGRESS_MASK 0x00000002
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#define DP_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK 0x00000004
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#define DP_REPLY_STATUS 0x014C
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#define DP_AUX_MAX_TIMEOUT_COUNT 50
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#define DP_AUX_MAX_DEFER_COUNT 50
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#define DP_AUX_ADDRESS 0x0108
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#define DP_AUX_WRITE_FIFO 0x0104
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#define DP_AUX_CMD 0x0100
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#define DP_AUX_CMD_SHIFT 8
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#define DP_AUX_CMD_NBYTES_TRANSFER_MASK 0x0000000F
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#define DP_AUX_REPLY_CODE 0x0138
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#define DP_AUX_REPLY_CODE_DEFER 0x2
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#define DP_AUX_REPLY_CODE_I2C_DEFER 0x8
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#define DP_AUX_REPLY_CODE_NACK 0x1
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#define DP_AUX_REPLY_CODE_I2C_NACK 0x4
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#define DP_REPLY_DATA_COUNT 0x0148
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#define DP_AUX_REPLY_DATA 0x0134
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#define DP_LANE_COUNT_SET_1 0x01
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#define DP_LANE_COUNT_SET_2 0x02
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#define DP_MAXIMUM_PE_LEVEL 2
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#define DP_MAXIMUM_VS_LEVEL 3
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#define DP_MAIN_STREAM_MISC0_COMPONENT_FORMAT_RGB 0x0
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#define DP_MAIN_STREAM_MISC0_BDC_6BPC 0x0
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#define DP_MAIN_STREAM_MISC0_BDC_8BPC 0x1
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#define DP_MAIN_STREAM_MISC0_BDC_10BPC 0x2
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#define DP_MAIN_STREAM_MISC0_BDC_12BPC 0x3
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#define DP_MAIN_STREAM_MISC0_BDC_16BPC 0x4
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#define DP_MAIN_STREAM_MISC0_BDC_SHIFT 5
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#define DP_PHY_CONFIG_TX_PHY_8B10BEN_MASK 0x0010000
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#define DP_PHY_CONFIG_PHY_RESET_MASK 0x0000001
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#define DP_ENABLE_MAIN_STREAM 0x0084
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#define DP_SOFT_RESET 0x001C
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#define DP_MAIN_STREAM_HTOTAL 0x0180
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#define DP_MAIN_STREAM_VTOTAL 0x0184
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#define DP_MAIN_STREAM_POLARITY 0x0188
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#define DP_MAIN_STREAM_POLARITY_VSYNC_POL_SHIFT 1
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#define DP_MAIN_STREAM_HSWIDTH 0x018C
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#define DP_MAIN_STREAM_VSWIDTH 0x0190
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#define DP_MAIN_STREAM_HRES 0x0194
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#define DP_MAIN_STREAM_VRES 0x0198
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#define DP_MAIN_STREAM_HSTART 0x019C
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#define DP_MAIN_STREAM_VSTART 0x01A0
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#define DP_MAIN_STREAM_MISC0 0x01A4
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#define DP_MAIN_STREAM_MISC1 0x01A8
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#define DP_M_VID 0x01AC
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#define DP_N_VID 0x01B4
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#define DP_USER_PIXEL_WIDTH 0x01B8
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#define DP_USER_DATA_COUNT_PER_LANE 0x01BC
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#define DP_TU_SIZE 0x01B0
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#define DP_MIN_BYTES_PER_TU 0x01C4
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#define DP_FRAC_BYTES_PER_TU 0x01C8
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#define DP_INIT_WAIT 0x01CC
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#define DP_PHY_CLOCK_SELECT_162GBPS 0x1
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#define DP_PHY_CLOCK_SELECT_270GBPS 0x3
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#define DP_PHY_CLOCK_SELECT_540GBPS 0x5
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#define DP_PHY_STATUS 0x0280
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#define DP_PHY_STATUS_ALL_LANES_READY_MASK 0x00000013
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#define DP_PHY_STATUS_GT_PLL_LOCK_MASK 0x00000010
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#define DP_PHY_STATUS_RESET_LANE_0_DONE_MASK 0x00000001
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#define DP_INTR_HPD_IRQ_MASK 0x00000001
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#define DP_INTR_MASK 0x03A4
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#define DP_DP_ENABLE 0x1
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#define DP_PHY_CONFIG_GT_ALL_RESET_MASK 0x0000003
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#define DP_PHY_CLOCK_SELECT 0x0234
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#define DP_AUX_CLK_DIVIDER_VAL_MASK 0x000000FF
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#define DP_AUX_CLK_DIVIDER 0x010C
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#define DP_DISABLE 0x0
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#define DP_ENABLE 0x0080
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#define DP_SOFT_RESET_EN 0x1
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#define DP_PHY_CONFIG 0x0200
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#define DP_REPLY_STATUS_REPLY_RECEIVED_MASK 0x00000001
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#define DP_REPLY_STATUS_REPLY_IN_PROGRESS_MASK 0x00000002
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#define DP_REPLY_STATUS_REPLY_ERROR_MASK 0x00000008
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#define DP_AUX_MAX_WAIT 20000
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#define DP_DPCD_SINK_COUNT 0x00200
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#define DP_DPCD_TP_SET_SCRAMB_DIS_MASK 0x20
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#define DP_DPCD_STATUS_LANE_1_CR_DONE_MASK 0x10
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#define DP_DPCD_STATUS_LANE_0_CR_DONE_MASK 0x01
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#define DP_DPCD_STATUS_LANE_1_CE_DONE_MASK 0x20
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#define DP_DPCD_STATUS_LANE_0_CE_DONE_MASK 0x02
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#define DP_DPCD_STATUS_LANE_1_SL_DONE_MASK 0x40
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#define DP_DPCD_STATUS_LANE_0_SL_DONE_MASK 0x04
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#define DP_DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK 0x01
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#define DP_DPCD_ADJ_REQ_LANE_0_2_VS_MASK 0x03
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#define DP_DPCD_ADJ_REQ_LANE_1_3_VS_MASK 0x30
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#define DP_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT 4
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#define DP_DPCD_ADJ_REQ_LANE_0_2_PE_MASK 0x0C
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#define DP_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT 2
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#define DP_DPCD_ADJ_REQ_LANE_1_3_PE_MASK 0xC0
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#define DP_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT 6
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#define DP_DPCD_TRAINING_LANE0_SET 0x00103
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#define DP_DPCD_TRAINING_LANEX_SET_MAX_VS_MASK 0x04
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#define DP_DPCD_TRAINING_LANEX_SET_MAX_PE_MASK 0x20
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#define DP_DPCD_TRAINING_LANEX_SET_PE_SHIFT 3
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#define DP_DPCD_SET_POWER_DP_PWR_VOLTAGE 0x00600
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#define DP_DPCD_RECEIVER_CAP_FIELD_START 0x00000
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#define DP_DPCD_MAX_LINK_RATE 0x00001
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#define DP_DPCD_MAX_LANE_COUNT 0x00002
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#define DP_DPCD_MAX_LANE_COUNT_MASK 0x1F
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#define DP_DPCD_ENHANCED_FRAME_SUPPORT_MASK 0x80
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#define DP_DPCD_MAX_DOWNSPREAD 0x00003
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#define DP_DPCD_MAX_DOWNSPREAD_MASK 0x01
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#define DP_DPCD_LANE_COUNT_SET 0x00101
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#define DP_DPCD_ENHANCED_FRAME_EN_MASK 0x80
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#define DP_DPCD_LINK_BW_SET 0x00100
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#define DP_DPCD_DOWNSPREAD_CTRL 0x00107
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#define DP_DPCD_SPREAD_AMP_MASK 0x10
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#define DP_DPCD_LANE_COUNT_SET_MASK 0x1F
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#define DP_DPCD_TPS3_SUPPORT_MASK 0x40
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#define DP_DPCD_TRAIN_AUX_RD_INTERVAL 0x0000E
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#define DP_DPCD_SINK_COUNT_HIGH_MASK 0x80
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#define DP_DPCD_SINK_COUNT_HIGH_LOW_SHIFT 1
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#define DP_DPCD_SINK_COUNT_LOW_MASK 0x3F
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#define DP_DPCD_TP_SET 0x00102
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#define SERDES_BASEADDR 0xFD400000
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#define SERDES_L0_TX_MARGININGF 0x0CC0
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#define SERDES_L0_TX_DEEMPHASIS 0x0048
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#define SERDES_LANE_OFFSET 0x4000
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#define DPDMA_TRIGGER_EN 1U
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#define DPDMA_RETRIGGER_EN 2U
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#define DPDMA_DESC_PREAMBLE 0xA5U
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#define DPDMA_DESC_IGNR_DONE 0x400U
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#define DPDMA_DESC_LAST_FRAME 0x200000U
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#define DPDMA_DESCRIPTOR_LINE_SIZE_STRIDE_SHIFT 18
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#define DPDMA_DESCRIPTOR_SRC_ADDR_WIDTH 32U
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#define DPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_SHIFT 16U
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#define DPDMA_CH0_DSCR_STRT_ADDR 0X0204U
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#define DPDMA_CH_OFFSET 0x100U
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#define DPDMA_CH0_CNTL 0x0218U
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#define DPDMA_CH3_CNTL 0x0518U
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#define DPDMA_CH0_DSCR_STRT_ADDRE 0x0200U
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#define DPDMA_CH3_DSCR_STRT_ADDR 0x0504
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#define DPDMA_CH3_DSCR_STRT_ADDRE 0x0500
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#define DPDMA_CH_CNTL_EN_MASK 0x1U
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#define DPDMA_CH_CNTL_PAUSE_MASK 0x2U
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#define DPDMA_GBL 0x0104U
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#define DPDMA_GBL_TRG_CH3_MASK 0x8
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#define DPDMA_TRIGGER_DONE 0U
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#define DPDMA_CH_CNTL_EN_MASK 0x1U
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#define DPDMA_CH_CNTL_PAUSE_MASK 0x2U
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#define DPDMA_CH_CNTL_QOS_DATA_RD_SHIFT 10U
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#define DPDMA_CH_CNTL_QOS_DATA_RD_MASK 0x3C00U
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#define DPDMA_CH_CNTL_QOS_DSCR_RD_SHIFT 6U
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#define DPDMA_CH_CNTL_QOS_DSCR_RD_MASK 0x03C0U
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#define DPDMA_CH_CNTL_QOS_DSCR_WR_SHIFT 2U
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#define DPDMA_CH_CNTL_QOS_DSCR_WR_MASK 0x3CU
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#define DPDMA_CH_OFFSET 0x100U
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#define DPDMA_WAIT_TIMEOUT 10000U
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#define DPDMA_AUDIO_ALIGNMENT 128U
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#define DPDMA_VIDEO_CHANNEL0 0U
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#define DPDMA_VIDEO_CHANNEL1 1U
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#define DPDMA_VIDEO_CHANNEL2 2U
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#define DPDMA_GRAPHICS_CHANNEL 3U
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#define DPDMA_AUDIO_CHANNEL0 4U
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#define DPDMA_AUDIO_CHANNEL1 5U
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#define DPDMA_DESC_PREAMBLE 0xA5U
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#define DPDMA_DESC_IGNR_DONE 0x400U
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#define DPDMA_DESC_UPDATE 0x200U
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#define DPDMA_DESC_COMP_INTR 0x100U
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#define DPDMA_DESC_LAST_FRAME 0x200000U
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#define DPDMA_DESC_DONE_SHIFT 31U
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#define DPDMA_QOS_MIN 4U
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#define DPDMA_QOS_MAX 11U
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#define DPDMA_BASE_ADDRESS 0xFD4C0000
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#define DPDMA_ISR 0x0004U
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#define DPDMA_IEN 0x000CU
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#define DPDMA_ISR_VSYNC_INT_MASK 0x08000000
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#define CLK_FPD_BASEADDR 0xFD1A0000
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#define VIDEO_REF_CTRL 0x00000070
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#define VIDEO_REF_CTRL_SRCSEL_MASK 0x00000007
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#define PLL_OUT_FREQ 1450000000
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#define INPUT_FREQ_PRECISION 100
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#define PRECISION 16
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#define SHIFT_DECIMAL BIT(16)
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#define ENABLE_BIT 1
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#define DISABLE_BIT 0
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#define PLL_CTRL_BYPASS_SHIFT 3
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#define PLL_CTRL_FBDIV_SHIFT 8
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#define PLL_CTRL_DIV2_SHIFT 16
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#define PLL_CTRL_PRE_SRC_SHIFT 20
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#define PLL_CTRL 0x00000020
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#define VPLL_CTRL 0x00000038
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#define PLL_CFG 0x00000024
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#define VPLL 2
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#define VPLL_CFG 0x0000003C
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#define VPLL_CFG_CP 4
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#define VPLL_CFG_RES 6
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#define VPLL_CFG_LFHF 3
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#define VPLL_CFG_LOCK_DLY 63
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#define VPLL_CFG_LOCK_CNT 600
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#define PLL_STATUS_VPLL_LOCK 2
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#define PLL_CFG_CP_SHIFT 5
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#define PLL_CFG_RES_SHIFT 0
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#define PLL_CFG_LFHF_SHIFT 10
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#define PLL_CFG_LOCK_DLY_SHIFT 25
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#define PLL_CFG_LOCK_CNT_SHIFT 13
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#define PLL_FRAC_CFG 0x00000028
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#define VPLL_FRAC_CFG 0x00000040
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#define PLL_FRAC_CFG_ENABLED_SHIFT 31
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#define PLL_FRAC_CFG_DATA_SHIFT 0
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#define PLL_CTRL_RESET_MASK 0x00000001
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#define PLL_CTRL_RESET_SHIFT 0
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#define PLL_STATUS 0x00000044
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#define REG_OFFSET 4
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#define PLL_CTRL_BYPASS_MASK 0x00000008
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#define PLL_CTRL_BYPASS_SHIFT 3
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#define DOMAIN_SWITCH_CTRL 0x00000044
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#define DOMAIN_SWITCH_DIVISOR0_MASK 0x00003F00
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#define DOMAIN_SWITCH_DIVISOR0_SHIFT 8
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#define VIDEO_REF_CTRL_CLKACT_MASK 0x01000000
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#define VIDEO_REF_CTRL_CLKACT_SHIFT 24
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#define VIDEO_REF_CTRL_DIVISOR1_MASK 0x003F0000
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#define VIDEO_REF_CTRL_DIVISOR1_SHIFT 16
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#define VIDEO_REF_CTRL_DIVISOR0_MASK 0x00003F00
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#define VIDEO_REF_CTRL_DIVISOR0_SHIFT 8
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#define PSS_REF_CLK 0
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#define FPD_CTRL_OFFSET 12
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#define VIDC_VM_NUM_SUPPORTED 2
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static const u32 vs[4][4] = {
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{ 0x2a, 0x27, 0x24, 0x20 },
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{ 0x27, 0x23, 0x20, 0xff },
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|
{ 0x24, 0x20, 0xff, 0xff },
|
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{ 0xff, 0xff, 0xff, 0xff },
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|
};
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|
|
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static const u32 pe[4][4] = {
|
|
{ 0x02, 0x02, 0x02, 0x02 },
|
|
{ 0x01, 0x01, 0x01, 0xff },
|
|
{ 0x00, 0x00, 0xff, 0xff },
|
|
{ 0xff, 0xff, 0xff, 0xff },
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|
};
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|
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const struct video_timing_mode vidc_video_timing_modes[VIDC_VM_NUM_SUPPORTED] = {
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{ VIDC_VM_640x480_60_P, "640x480@60Hz", VIDC_FR_60HZ,
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{640, 16, 96, 48, 800, 0,
|
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480, 10, 2, 33, 525, 0, 0, 0, 0, 0} },
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|
{ VIDC_VM_1024x768_60_P, "1024x768@60Hz", VIDC_FR_60HZ,
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{1024, 24, 136, 160, 1344, 0,
|
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768, 3, 6, 29, 806, 0, 0, 0, 0, 0} },
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};
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|
|
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const struct av_buf_vid_attribute avbuf_supported_formats[] = {
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|
/* Non-Live Graphics formats */
|
|
{ RGBA8888, 0, INTERLEAVED,
|
|
{AVBUF_BUF_8BIT_SF, AVBUF_BUF_8BIT_SF, AVBUF_BUF_8BIT_SF},
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|
0, 1, 0, 32},
|
|
};
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#endif
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