mirror of
https://github.com/AsahiLinux/u-boot
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ffff21fb27
Fix a typo in a comment. Signed-off-by: Simon Glass <sjg@chromium.org>
193 lines
5.1 KiB
C
193 lines
5.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <common.h>
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#include <handoff.h>
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#include <init.h>
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#include <log.h>
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#include <asm/fsp/fsp_support.h>
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#include <asm/e820.h>
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#include <asm/global_data.h>
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#include <asm/mrccache.h>
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#include <asm/mtrr.h>
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#include <asm/post.h>
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#include <dm/ofnode.h>
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DECLARE_GLOBAL_DATA_PTR;
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int fsp_scan_for_ram_size(void)
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{
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phys_size_t ram_size = 0;
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const struct hob_header *hdr;
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struct hob_res_desc *res_desc;
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hdr = gd->arch.hob_list;
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while (!end_of_hob(hdr)) {
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if (hdr->type == HOB_TYPE_RES_DESC) {
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res_desc = (struct hob_res_desc *)hdr;
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if (res_desc->type == RES_SYS_MEM ||
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res_desc->type == RES_MEM_RESERVED)
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ram_size += res_desc->len;
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}
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hdr = get_next_hob(hdr);
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}
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gd->ram_size = ram_size;
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post_code(POST_DRAM);
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return 0;
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};
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int dram_init_banksize(void)
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{
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efi_guid_t fsp = FSP_HOB_RESOURCE_OWNER_FSP_GUID;
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const struct hob_header *hdr;
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struct hob_res_desc *res_desc;
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phys_addr_t mtrr_top;
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phys_addr_t low_end;
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uint bank;
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bool update_mtrr;
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/*
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* For FSP1, the system memory and reserved memory used by FSP are
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* already programmed in the MTRR by FSP. Also it is observed that
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* FSP on Intel Queensbay platform reports the TSEG memory range
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* that has the same RES_MEM_RESERVED resource type whose address
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* is programmed by FSP to be near the top of 4 GiB space, which is
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* not what we want for DRAM.
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*
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* However it seems FSP2's behavior is different. We need to add the
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* DRAM range in MTRR otherwise the boot process goes very slowly,
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* which was observed on Chromebook Coral with FSP2.
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*/
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update_mtrr = CONFIG_IS_ENABLED(FSP_VERSION2);
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if (!ll_boot_init()) {
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gd->bd->bi_dram[0].start = 0;
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gd->bd->bi_dram[0].size = gd->ram_size;
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if (update_mtrr)
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mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size);
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return 0;
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}
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low_end = 0; /* top of low memory usable by U-Boot */
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mtrr_top = 0; /* top of low memory (even if reserved) */
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for (bank = 1, hdr = gd->arch.hob_list;
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bank < CONFIG_NR_DRAM_BANKS && !end_of_hob(hdr);
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hdr = get_next_hob(hdr)) {
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if (hdr->type != HOB_TYPE_RES_DESC)
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continue;
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res_desc = (struct hob_res_desc *)hdr;
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if (!guidcmp(&res_desc->owner, &fsp))
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low_end = res_desc->phys_start;
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if (res_desc->type != RES_SYS_MEM &&
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res_desc->type != RES_MEM_RESERVED)
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continue;
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if (res_desc->phys_start < (1ULL << 32)) {
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mtrr_top = max(mtrr_top,
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res_desc->phys_start + res_desc->len);
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} else {
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gd->bd->bi_dram[bank].start = res_desc->phys_start;
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gd->bd->bi_dram[bank].size = res_desc->len;
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if (update_mtrr)
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mtrr_add_request(MTRR_TYPE_WRBACK,
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res_desc->phys_start,
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res_desc->len);
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log_debug("ram %llx %llx\n",
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gd->bd->bi_dram[bank].start,
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gd->bd->bi_dram[bank].size);
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}
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}
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/* Add the memory below 4GB */
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gd->bd->bi_dram[0].start = 0;
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gd->bd->bi_dram[0].size = low_end;
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/*
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* Set up an MTRR to the top of low, reserved memory. This is necessary
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* for graphics to run at full speed in U-Boot.
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*/
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if (update_mtrr)
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mtrr_add_request(MTRR_TYPE_WRBACK, 0, mtrr_top);
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return 0;
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}
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unsigned int install_e820_map(unsigned int max_entries,
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struct e820_entry *entries)
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{
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unsigned int num_entries = 0;
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const struct hob_header *hdr;
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struct hob_res_desc *res_desc;
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const fdt64_t *prop;
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int size;
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hdr = gd->arch.hob_list;
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while (!end_of_hob(hdr)) {
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if (hdr->type == HOB_TYPE_RES_DESC) {
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res_desc = (struct hob_res_desc *)hdr;
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entries[num_entries].addr = res_desc->phys_start;
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entries[num_entries].size = res_desc->len;
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if (res_desc->type == RES_SYS_MEM)
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entries[num_entries].type = E820_RAM;
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else if (res_desc->type == RES_MEM_RESERVED)
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entries[num_entries].type = E820_RESERVED;
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num_entries++;
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}
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hdr = get_next_hob(hdr);
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}
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/* Mark PCIe ECAM address range as reserved */
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entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE;
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entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE;
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entries[num_entries].type = E820_RESERVED;
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num_entries++;
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if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
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ulong stack_size;
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stack_size = CONFIG_IS_ENABLED(HAVE_ACPI_RESUME,
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(CONFIG_STACK_SIZE_RESUME), (0));
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/*
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* Everything between U-Boot's stack and ram top needs to be
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* reserved in order for ACPI S3 resume to work.
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*/
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entries[num_entries].addr = gd->start_addr_sp - stack_size;
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entries[num_entries].size = gd->ram_top - gd->start_addr_sp +
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stack_size;
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entries[num_entries].type = E820_RESERVED;
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num_entries++;
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}
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prop = ofnode_read_chosen_prop("e820-entries", &size);
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if (prop) {
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int count = size / (sizeof(u64) * 3);
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int i;
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if (num_entries + count >= max_entries)
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return -ENOSPC;
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for (i = 0; i < count; i++, num_entries++, prop += 3) {
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entries[num_entries].addr = fdt64_to_cpu(prop[0]);
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entries[num_entries].size = fdt64_to_cpu(prop[1]);
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entries[num_entries].type = fdt64_to_cpu(prop[2]);
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}
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}
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return num_entries;
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}
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#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB)
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int handoff_arch_save(struct spl_handoff *ho)
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{
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ho->arch.usable_ram_top = gd->bd->bi_dram[0].size;
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ho->arch.hob_list = gd->arch.hob_list;
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return 0;
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}
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#endif
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