mirror of
https://github.com/AsahiLinux/u-boot
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db5741f7a8
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get system manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
166 lines
3.3 KiB
C
166 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
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*
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*/
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#include <altera.h>
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#include <common.h>
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#include <env.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/system_manager.h>
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#include <asm/arch/misc.h>
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#include <asm/pl310.h>
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#include <linux/libfdt.h>
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#include <asm/arch/mailbox_s10.h>
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#include <dt-bindings/reset/altr,rst-mgr-s10.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* FPGA programming support for SoC FPGA Stratix 10
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*/
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static Altera_desc altera_fpga[] = {
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{
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/* Family */
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Intel_FPGA_Stratix10,
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/* Interface type */
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secure_device_manager_mailbox,
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/* No limitation as additional data will be ignored */
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-1,
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/* No device function table */
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NULL,
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/* Base interface address specified in driver */
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NULL,
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/* No cookie implementation */
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0
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},
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};
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/*
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* DesignWare Ethernet initialization
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*/
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#ifdef CONFIG_ETH_DESIGNWARE
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static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode)
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{
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u32 modereg;
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if (!phymode)
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return -EINVAL;
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if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii") ||
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!strcmp(phymode, "sgmii"))
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modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
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else if (!strcmp(phymode, "rgmii"))
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modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
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else if (!strcmp(phymode, "rmii"))
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modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
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else
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return -EINVAL;
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clrsetbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_S10_EMAC0 +
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gmac_index,
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SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg);
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return 0;
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}
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static int socfpga_set_phymode(void)
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{
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const void *fdt = gd->fdt_blob;
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struct fdtdec_phandle_args args;
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const char *phy_mode;
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u32 gmac_index;
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int nodes[3]; /* Max. 3 GMACs */
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int ret, count;
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int i, node;
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count = fdtdec_find_aliases_for_id(fdt, "ethernet",
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COMPAT_ALTERA_SOCFPGA_DWMAC,
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nodes, ARRAY_SIZE(nodes));
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for (i = 0; i < count; i++) {
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node = nodes[i];
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if (node <= 0)
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continue;
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ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
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"#reset-cells", 1, 0,
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&args);
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if (ret || args.args_count != 1) {
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debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
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continue;
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}
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gmac_index = args.args[0] - EMAC0_RESET;
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phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
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ret = socfpga_phymode_setup(gmac_index, phy_mode);
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if (ret) {
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debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
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continue;
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}
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}
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return 0;
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}
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#else
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static int socfpga_set_phymode(void)
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{
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return 0;
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};
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#endif
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/*
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* Print CPU information
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*/
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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puts("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n");
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return 0;
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}
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#endif
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#ifdef CONFIG_ARCH_MISC_INIT
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int arch_misc_init(void)
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{
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char qspi_string[13];
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sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
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env_set("qspi_clock", qspi_string);
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socfpga_set_phymode();
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return 0;
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}
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#endif
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int arch_early_init_r(void)
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{
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socfpga_fpga_add(&altera_fpga[0]);
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return 0;
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}
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void do_bridge_reset(int enable, unsigned int mask)
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{
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/* Check FPGA status before bridge enable */
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if (enable) {
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int ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS);
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if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
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ret = mbox_get_fpga_config_status(MBOX_CONFIG_STATUS);
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if (ret)
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return;
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}
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socfpga_bridges_reset(enable);
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}
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