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The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
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| .. | ||
| clk-am3-dpll-x2.c | ||
| clk-am3-dpll.c | ||
| clk-ctrl.c | ||
| clk-divider.c | ||
| clk-gate.c | ||
| clk-k3-pll.c | ||
| clk-k3.c | ||
| clk-mux.c | ||
| clk-sci.c | ||
| clk.c | ||
| clk.h | ||
| Kconfig | ||
| Makefile | ||
| omap4-cm.c | ||