mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-29 08:01:08 +00:00
b4c2c151b1
default n/no doesn't need to be specified. It is default option anyway. Signed-off-by: Michal Simek <michal.simek@xilinx.com> [trini: Rework FSP_USE_UPD portion] Signed-off-by: Tom Rini <trini@konsulko.com>
45 lines
769 B
Text
45 lines
769 B
Text
menu "Xtensa architecture"
|
|
depends on XTENSA
|
|
|
|
config SYS_ARCH
|
|
string
|
|
default "xtensa"
|
|
|
|
config SYS_CPU
|
|
string "Xtensa Core Variant"
|
|
|
|
choice
|
|
prompt "Target select"
|
|
|
|
config TARGET_XTFPGA
|
|
bool "Support XTFPGA"
|
|
|
|
endchoice
|
|
|
|
config SYS_ICACHE_OFF
|
|
bool "Do not enable icache"
|
|
help
|
|
Do not enable instruction cache in U-Boot.
|
|
|
|
config SPL_SYS_ICACHE_OFF
|
|
bool "Do not enable icache in SPL"
|
|
depends on SPL
|
|
default SYS_ICACHE_OFF
|
|
help
|
|
Do not enable instruction cache in SPL.
|
|
|
|
config SYS_DCACHE_OFF
|
|
bool "Do not enable dcache"
|
|
help
|
|
Do not enable data cache in U-Boot.
|
|
|
|
config SPL_SYS_DCACHE_OFF
|
|
bool "Do not enable dcache in SPL"
|
|
depends on SPL
|
|
default SYS_DCACHE_OFF
|
|
help
|
|
Do not enable data cache in SPL.
|
|
|
|
source "board/cadence/xtfpga/Kconfig"
|
|
|
|
endmenu
|