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https://github.com/AsahiLinux/u-boot
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caa4daa2ae
We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
237 lines
5.3 KiB
C
237 lines
5.3 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Microsemi SoCs spi driver
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*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <log.h>
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#include <malloc.h>
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#include <spi.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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struct mscc_bb_priv {
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void __iomem *regs;
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u32 deactivate_delay_us;
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bool cs_active; /* State flag as to whether CS is asserted */
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int cs_num;
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u32 svalue; /* Value to start transfer with */
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u32 clk1; /* Clock value start */
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u32 clk2; /* Clock value 2nd phase */
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};
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/* Delay 24 instructions for this particular application */
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#define hold_time_delay() mscc_vcoreiii_nop_delay(3)
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static int mscc_bb_spi_cs_activate(struct mscc_bb_priv *priv, int mode, int cs)
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{
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if (!priv->cs_active) {
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int cpha = mode & SPI_CPHA;
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u32 cs_value;
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priv->cs_num = cs;
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if (cpha) {
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/* Initial clock starts SCK=1 */
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priv->clk1 = ICPU_SW_MODE_SW_SPI_SCK;
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priv->clk2 = 0;
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} else {
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/* Initial clock starts SCK=0 */
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priv->clk1 = 0;
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priv->clk2 = ICPU_SW_MODE_SW_SPI_SCK;
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}
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/* Enable bitbang, SCK_OE, SDO_OE */
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priv->svalue = (ICPU_SW_MODE_SW_PIN_CTRL_MODE | /* Bitbang */
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ICPU_SW_MODE_SW_SPI_SCK_OE | /* SCK_OE */
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ICPU_SW_MODE_SW_SPI_SDO_OE); /* SDO OE */
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/* Add CS */
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if (cs >= 0) {
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cs_value =
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ICPU_SW_MODE_SW_SPI_CS_OE(BIT(cs)) |
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ICPU_SW_MODE_SW_SPI_CS(BIT(cs));
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} else {
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cs_value = 0;
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}
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priv->svalue |= cs_value;
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/* Enable the CS in HW, Initial clock value */
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writel(priv->svalue | priv->clk2, priv->regs);
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priv->cs_active = true;
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debug("Activated CS%d\n", priv->cs_num);
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}
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return 0;
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}
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static int mscc_bb_spi_cs_deactivate(struct mscc_bb_priv *priv, int deact_delay)
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{
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if (priv->cs_active) {
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/* Keep driving the CLK to its current value while
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* actively deselecting CS.
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*/
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u32 value = readl(priv->regs);
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value &= ~ICPU_SW_MODE_SW_SPI_CS_M;
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writel(value, priv->regs);
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hold_time_delay();
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/* Stop driving the clock, but keep CS with nCS == 1 */
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value &= ~ICPU_SW_MODE_SW_SPI_SCK_OE;
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writel(value, priv->regs);
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/* Deselect hold time delay */
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if (deact_delay)
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udelay(deact_delay);
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/* Drop everything */
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writel(0, priv->regs);
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priv->cs_active = false;
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debug("Deactivated CS%d\n", priv->cs_num);
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}
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return 0;
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}
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int mscc_bb_spi_claim_bus(struct udevice *dev)
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{
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return 0;
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}
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int mscc_bb_spi_release_bus(struct udevice *dev)
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{
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return 0;
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}
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int mscc_bb_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct dm_spi_slave_platdata *plat = dev_get_parent_plat(dev);
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struct mscc_bb_priv *priv = dev_get_priv(bus);
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u32 i, count;
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const u8 *txd = dout;
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u8 *rxd = din;
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debug("spi_xfer: slave %s:%s cs%d mode %d, dout %p din %p bitlen %u\n",
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dev->parent->name, dev->name, plat->cs, plat->mode, dout,
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din, bitlen);
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if (flags & SPI_XFER_BEGIN)
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mscc_bb_spi_cs_activate(priv, plat->mode, plat->cs);
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count = bitlen / 8;
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for (i = 0; i < count; i++) {
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u32 rx = 0, mask = 0x80, value;
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while (mask) {
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/* Initial condition: CLK is low. */
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value = priv->svalue;
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if (txd && txd[i] & mask)
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value |= ICPU_SW_MODE_SW_SPI_SDO;
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/* Drive data while taking CLK low. The device
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* we're accessing will sample on the
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* following rising edge and will output data
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* on this edge for us to be sampled at the
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* end of this loop.
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*/
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writel(value | priv->clk1, priv->regs);
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/* Wait for t_setup. All devices do have a
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* setup-time, so we always insert some delay
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* here. Some devices have a very long
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* setup-time, which can be adjusted by the
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* user through vcoreiii_device->delay.
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*/
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hold_time_delay();
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/* Drive the clock high. */
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writel(value | priv->clk2, priv->regs);
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/* Wait for t_hold. See comment about t_setup
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* above.
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*/
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hold_time_delay();
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/* We sample as close to the next falling edge
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* as possible.
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*/
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value = readl(priv->regs);
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if (value & ICPU_SW_MODE_SW_SPI_SDI)
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rx |= mask;
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mask >>= 1;
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}
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if (rxd) {
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debug("Read 0x%02x\n", rx);
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rxd[i] = (u8)rx;
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}
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debug("spi_xfer: byte %d/%d\n", i + 1, count);
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}
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debug("spi_xfer: done\n");
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if (flags & SPI_XFER_END)
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mscc_bb_spi_cs_deactivate(priv, priv->deactivate_delay_us);
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return 0;
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}
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int mscc_bb_spi_set_speed(struct udevice *dev, unsigned int speed)
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{
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/* Accept any speed */
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return 0;
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}
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int mscc_bb_spi_set_mode(struct udevice *dev, unsigned int mode)
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{
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return 0;
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}
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static const struct dm_spi_ops mscc_bb_ops = {
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.claim_bus = mscc_bb_spi_claim_bus,
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.release_bus = mscc_bb_spi_release_bus,
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.xfer = mscc_bb_spi_xfer,
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.set_speed = mscc_bb_spi_set_speed,
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.set_mode = mscc_bb_spi_set_mode,
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};
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static const struct udevice_id mscc_bb_ids[] = {
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{ .compatible = "mscc,luton-bb-spi" },
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{ }
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};
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static int mscc_bb_spi_probe(struct udevice *bus)
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{
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struct mscc_bb_priv *priv = dev_get_priv(bus);
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debug("%s: loaded, priv %p\n", __func__, priv);
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priv->regs = (void __iomem *)dev_read_addr(bus);
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priv->deactivate_delay_us =
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dev_read_u32_default(bus, "spi-deactivate-delay", 0);
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priv->cs_active = false;
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return 0;
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}
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U_BOOT_DRIVER(mscc_bb) = {
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.name = "mscc_bb",
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.id = UCLASS_SPI,
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.of_match = mscc_bb_ids,
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.ops = &mscc_bb_ops,
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.priv_auto = sizeof(struct mscc_bb_priv),
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.probe = mscc_bb_spi_probe,
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};
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