Jagan Teki 4f3cc17d38 ram: rk3399: Add LPPDDR4-400 timings inc ... LPDDR4 initialization start with at board selected frequency and then it switches into 400MHz and 800MHz simultaneously to make the proper sequence work on each channel with associated training. So, add LPDDR4-400 timings inc file in driver area so-that these timings will take during LPDDR4 initialization phase. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>		2019-07-21 00:00:27 +08:00
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dmc-rk3368.c	rockchip: dmc: rk3368: update rank number for evb-px5	2019-05-08 17:34:12 +08:00
Kconfig	ram: rockchip: Kconfig: Add RK3399 LPDDR4 entry	2019-07-20 23:59:44 +08:00
Makefile	ram: rockchip: Add debug sdram driver	2019-07-19 11:11:09 +08:00
sdram-rk3399-lpddr4-400.inc	ram: rk3399: Add LPPDDR4-400 timings inc	2019-07-21 00:00:27 +08:00
sdram_debug.c	ram: rk3399: debug: Add sdram_print_stride	2019-07-19 11:11:10 +08:00
sdram_rk322x.c	Revert "rockchip: rk322x: ram: enable DRAM init in SPL instead of TPL"	2019-05-08 17:34:12 +08:00
sdram_rk3128.c	rockchip: use 'arch-rockchip' as header file path	2019-05-01 00:00:05 +02:00
sdram_rk3188.c	rockchip: use 'arch-rockchip' as header file path	2019-05-01 00:00:05 +02:00
sdram_rk3288.c	rockchip: use 'arch-rockchip' as header file path	2019-05-01 00:00:05 +02:00
sdram_rk3328.c	rockchip: use 'arch-rockchip' as header file path	2019-05-01 00:00:05 +02:00
sdram_rk3399.c	ram: rk3399: Add LPPDR4 mr detection	2019-07-21 00:00:10 +08:00