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https://github.com/AsahiLinux/u-boot
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1b4c3e6125
For SOM with the EC configuration, the ethernet PHY is located on the SOM itself, and connected to the CPU ethernet controller. It has a reset line controlled via GPIO1_IO9. In this configuration, the PHY located on the carrier board is not connected to anything and is therefore not used. For SOM without EC configuration, the ethernet PHY on the carrier board is connected to the CPU ethernet controller. It has a reset line controlled via the GPIO expander PCA9534_IO5. The hardware configuration (EC) is determined at runtime by reading from the SOM EEPROM. To support both hardware configurations (EC and non-EC), adjust/fix the PHY reset gpios according to the hardware configuration read at runtime from the SOM EEPROM. This adjustement is done in U-Boot (OF_BOARD_FIXUP) and kernel (OF_BOARD_SETUP) device trees. Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
236 lines
5.1 KiB
Text
236 lines
5.1 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2019-2020 Variscite Ltd.
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* Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
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*/
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/dts-v1/;
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#include "imx8mn-var-som.dtsi"
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/ {
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model = "Variscite VAR-SOM-MX8MN Symphony evaluation board";
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compatible = "variscite,var-som-mx8mn-symphony", "variscite,var-som-mx8mn", "fsl,imx8mn";
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reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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gpio-keys {
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compatible = "gpio-keys";
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key-back {
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label = "Back";
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gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_BACK>;
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};
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key-home {
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label = "Home";
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gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_HOME>;
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};
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key-menu {
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label = "Menu";
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gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_MENU>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led {
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label = "Heartbeat";
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gpios = <&pca9534 0 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "heartbeat";
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};
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};
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};
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&i2c2 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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pca9534: gpio@20 {
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compatible = "nxp,pca9534";
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reg = <0x20>;
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gpio-controller;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pca9534>;
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interrupt-parent = <&gpio1>;
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interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
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#gpio-cells = <2>;
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wakeup-source;
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/* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */
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usb3-sata-sel-hog {
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gpio-hog;
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gpios = <4 GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "usb3_sata_sel";
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};
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som-vselect-hog {
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gpio-hog;
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gpios = <6 GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "som_vselect";
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};
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enet-sel-hog {
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gpio-hog;
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gpios = <7 GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "enet_sel";
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};
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};
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extcon_usbotg1: typec@3d {
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compatible = "nxp,ptn5150";
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reg = <0x3d>;
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interrupt-parent = <&gpio1>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ptn5150>;
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status = "okay";
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};
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};
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&i2c3 {
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/* Capacitive touch controller */
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ft5x06_ts: touchscreen@38 {
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compatible = "edt,edt-ft5406";
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reg = <0x38>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_captouch>;
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interrupt-parent = <&gpio5>;
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interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
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touchscreen-size-x = <800>;
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touchscreen-size-y = <480>;
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touchscreen-inverted-x;
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touchscreen-inverted-y;
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};
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rtc@68 {
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compatible = "dallas,ds1337";
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reg = <0x68>;
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};
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};
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/* Header */
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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/* Header */
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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status = "okay";
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};
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&usbotg1 {
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disable-over-current;
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extcon = <&extcon_usbotg1>, <&extcon_usbotg1>;
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};
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&pinctrl_fec1 {
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fsl,pins = <
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MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
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MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
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MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
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MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
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MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
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MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
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MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
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MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
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MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
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MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
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MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
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MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
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MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
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MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
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/* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */
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>;
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};
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&pinctrl_fec1_sleep {
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fsl,pins = <
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MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x120
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MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120
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MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x120
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MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x120
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MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x120
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MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x120
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MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x120
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MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x120
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MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x120
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MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x120
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MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x120
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MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x120
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MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120
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MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120
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/* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */
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>;
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};
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&iomuxc {
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pinctrl_captouch: captouchgrp {
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fsl,pins = <
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MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x16
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
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MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
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>;
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};
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pinctrl_pca9534: pca9534grp {
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fsl,pins = <
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MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16
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>;
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};
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pinctrl_ptn5150: ptn5150grp {
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fsl,pins = <
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MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16
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>;
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};
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pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
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fsl,pins = <
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MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x41
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
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MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
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>;
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};
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pinctrl_uart3: uart3grp {
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fsl,pins = <
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MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
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MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
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>;
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};
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};
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