mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-20 11:43:22 +00:00
0807fe0a49
Common code already takes care of setting up these defines when a port hasn't specified them, so punt the duplicate values. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
716 lines
35 KiB
C
716 lines
35 KiB
C
/* DO NOT EDIT THIS FILE
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* Automatically generated by generate-def-headers.xsl
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* DO NOT EDIT THIS FILE
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*/
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#ifndef __BFIN_DEF_ADSP_BF561_proc__
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#define __BFIN_DEF_ADSP_BF561_proc__
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#include "../mach-common/ADSP-EDN-core_def.h"
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#define PLL_CTL 0xFFC00000
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#define PLL_DIV 0xFFC00004
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#define VR_CTL 0xFFC00008
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#define PLL_STAT 0xFFC0000C
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#define PLL_LOCKCNT 0xFFC00010
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#define CHIPID 0xFFC00014
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#define SPI_CTL 0xFFC00500
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#define SPI_FLG 0xFFC00504
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#define SPI_STAT 0xFFC00508
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#define SPI_TDBR 0xFFC0050C
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#define SPI_RDBR 0xFFC00510
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#define SPI_BAUD 0xFFC00514
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#define SPI_SHADOW 0xFFC00518
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#define WDOGA_CTL 0xFFC00200
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#define WDOGA_CNT 0xFFC00204
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#define WDOGA_STAT 0xFFC00208
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#define WDOGB_CTL 0xFFC01200
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#define WDOGB_CNT 0xFFC01204
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#define WDOGB_STAT 0xFFC01208
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#define DMA1_TC_PER 0xFFC01B0C /* Traffic Control Periods */
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#define DMA1_TC_CNT 0xFFC01B10 /* Traffic Control Current Counts */
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#define DMA1_0_CONFIG 0xFFC01C08
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#define DMA1_0_NEXT_DESC_PTR 0xFFC01C00
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#define DMA1_0_START_ADDR 0xFFC01C04
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#define DMA1_0_X_COUNT 0xFFC01C10
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#define DMA1_0_Y_COUNT 0xFFC01C18
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#define DMA1_0_X_MODIFY 0xFFC01C14
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#define DMA1_0_Y_MODIFY 0xFFC01C1C
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#define DMA1_0_CURR_DESC_PTR 0xFFC01C20
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#define DMA1_0_CURR_ADDR 0xFFC01C24
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#define DMA1_0_CURR_X_COUNT 0xFFC01C30
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#define DMA1_0_CURR_Y_COUNT 0xFFC01C38
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#define DMA1_0_IRQ_STATUS 0xFFC01C28
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#define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C
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#define DMA1_1_CONFIG 0xFFC01C48
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#define DMA1_1_NEXT_DESC_PTR 0xFFC01C40
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#define DMA1_1_START_ADDR 0xFFC01C44
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#define DMA1_1_X_COUNT 0xFFC01C50
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#define DMA1_1_Y_COUNT 0xFFC01C58
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#define DMA1_1_X_MODIFY 0xFFC01C54
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#define DMA1_1_Y_MODIFY 0xFFC01C5C
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#define DMA1_1_CURR_DESC_PTR 0xFFC01C60
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#define DMA1_1_CURR_ADDR 0xFFC01C64
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#define DMA1_1_CURR_X_COUNT 0xFFC01C70
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#define DMA1_1_CURR_Y_COUNT 0xFFC01C78
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#define DMA1_1_IRQ_STATUS 0xFFC01C68
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#define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C
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#define DMA1_2_CONFIG 0xFFC01C88
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#define DMA1_2_NEXT_DESC_PTR 0xFFC01C80
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#define DMA1_2_START_ADDR 0xFFC01C84
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#define DMA1_2_X_COUNT 0xFFC01C90
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#define DMA1_2_Y_COUNT 0xFFC01C98
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#define DMA1_2_X_MODIFY 0xFFC01C94
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#define DMA1_2_Y_MODIFY 0xFFC01C9C
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#define DMA1_2_CURR_DESC_PTR 0xFFC01CA0
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#define DMA1_2_CURR_ADDR 0xFFC01CA4
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#define DMA1_2_CURR_X_COUNT 0xFFC01CB0
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#define DMA1_2_CURR_Y_COUNT 0xFFC01CB8
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#define DMA1_2_IRQ_STATUS 0xFFC01CA8
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#define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC
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#define DMA1_3_CONFIG 0xFFC01CC8
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#define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0
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#define DMA1_3_START_ADDR 0xFFC01CC4
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#define DMA1_3_X_COUNT 0xFFC01CD0
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#define DMA1_3_Y_COUNT 0xFFC01CD8
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#define DMA1_3_X_MODIFY 0xFFC01CD4
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#define DMA1_3_Y_MODIFY 0xFFC01CDC
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#define DMA1_3_CURR_DESC_PTR 0xFFC01CE0
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#define DMA1_3_CURR_ADDR 0xFFC01CE4
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#define DMA1_3_CURR_X_COUNT 0xFFC01CF0
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#define DMA1_3_CURR_Y_COUNT 0xFFC01CF8
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#define DMA1_3_IRQ_STATUS 0xFFC01CE8
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#define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC
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#define DMA1_4_CONFIG 0xFFC01D08
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#define DMA1_4_NEXT_DESC_PTR 0xFFC01D00
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#define DMA1_4_START_ADDR 0xFFC01D04
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#define DMA1_4_X_COUNT 0xFFC01D10
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#define DMA1_4_Y_COUNT 0xFFC01D18
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#define DMA1_4_X_MODIFY 0xFFC01D14
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#define DMA1_4_Y_MODIFY 0xFFC01D1C
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#define DMA1_4_CURR_DESC_PTR 0xFFC01D20
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#define DMA1_4_CURR_ADDR 0xFFC01D24
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#define DMA1_4_CURR_X_COUNT 0xFFC01D30
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#define DMA1_4_CURR_Y_COUNT 0xFFC01D38
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#define DMA1_4_IRQ_STATUS 0xFFC01D28
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#define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C
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#define DMA1_5_CONFIG 0xFFC01D48
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#define DMA1_5_NEXT_DESC_PTR 0xFFC01D40
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#define DMA1_5_START_ADDR 0xFFC01D44
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#define DMA1_5_X_COUNT 0xFFC01D50
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#define DMA1_5_Y_COUNT 0xFFC01D58
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#define DMA1_5_X_MODIFY 0xFFC01D54
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#define DMA1_5_Y_MODIFY 0xFFC01D5C
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#define DMA1_5_CURR_DESC_PTR 0xFFC01D60
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#define DMA1_5_CURR_ADDR 0xFFC01D64
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#define DMA1_5_CURR_X_COUNT 0xFFC01D70
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#define DMA1_5_CURR_Y_COUNT 0xFFC01D78
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#define DMA1_5_IRQ_STATUS 0xFFC01D68
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#define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C
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#define DMA1_6_CONFIG 0xFFC01D88
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#define DMA1_6_NEXT_DESC_PTR 0xFFC01D80
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#define DMA1_6_START_ADDR 0xFFC01D84
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#define DMA1_6_X_COUNT 0xFFC01D90
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#define DMA1_6_Y_COUNT 0xFFC01D98
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#define DMA1_6_X_MODIFY 0xFFC01D94
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#define DMA1_6_Y_MODIFY 0xFFC01D9C
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#define DMA1_6_CURR_DESC_PTR 0xFFC01DA0
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#define DMA1_6_CURR_ADDR 0xFFC01DA4
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#define DMA1_6_CURR_X_COUNT 0xFFC01DB0
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#define DMA1_6_CURR_Y_COUNT 0xFFC01DB8
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#define DMA1_6_IRQ_STATUS 0xFFC01DA8
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#define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC
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#define DMA1_7_CONFIG 0xFFC01DC8
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#define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0
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#define DMA1_7_START_ADDR 0xFFC01DC4
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#define DMA1_7_X_COUNT 0xFFC01DD0
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#define DMA1_7_Y_COUNT 0xFFC01DD8
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#define DMA1_7_X_MODIFY 0xFFC01DD4
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#define DMA1_7_Y_MODIFY 0xFFC01DDC
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#define DMA1_7_CURR_DESC_PTR 0xFFC01DE0
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#define DMA1_7_CURR_ADDR 0xFFC01DE4
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#define DMA1_7_CURR_X_COUNT 0xFFC01DF0
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#define DMA1_7_CURR_Y_COUNT 0xFFC01DF8
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#define DMA1_7_IRQ_STATUS 0xFFC01DE8
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#define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC
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#define DMA1_8_CONFIG 0xFFC01E08
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#define DMA1_8_NEXT_DESC_PTR 0xFFC01E00
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#define DMA1_8_START_ADDR 0xFFC01E04
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#define DMA1_8_X_COUNT 0xFFC01E10
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#define DMA1_8_Y_COUNT 0xFFC01E18
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#define DMA1_8_X_MODIFY 0xFFC01E14
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#define DMA1_8_Y_MODIFY 0xFFC01E1C
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#define DMA1_8_CURR_DESC_PTR 0xFFC01E20
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#define DMA1_8_CURR_ADDR 0xFFC01E24
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#define DMA1_8_CURR_X_COUNT 0xFFC01E30
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#define DMA1_8_CURR_Y_COUNT 0xFFC01E38
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#define DMA1_8_IRQ_STATUS 0xFFC01E28
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#define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C
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#define DMA1_9_CONFIG 0xFFC01E48
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#define DMA1_9_NEXT_DESC_PTR 0xFFC01E40
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#define DMA1_9_START_ADDR 0xFFC01E44
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#define DMA1_9_X_COUNT 0xFFC01E50
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#define DMA1_9_Y_COUNT 0xFFC01E58
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#define DMA1_9_X_MODIFY 0xFFC01E54
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#define DMA1_9_Y_MODIFY 0xFFC01E5C
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#define DMA1_9_CURR_DESC_PTR 0xFFC01E60
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#define DMA1_9_CURR_ADDR 0xFFC01E64
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#define DMA1_9_CURR_X_COUNT 0xFFC01E70
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#define DMA1_9_CURR_Y_COUNT 0xFFC01E78
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#define DMA1_9_IRQ_STATUS 0xFFC01E68
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#define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C
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#define DMA1_10_CONFIG 0xFFC01E88
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#define DMA1_10_NEXT_DESC_PTR 0xFFC01E80
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#define DMA1_10_START_ADDR 0xFFC01E84
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#define DMA1_10_X_COUNT 0xFFC01E90
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#define DMA1_10_Y_COUNT 0xFFC01E98
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#define DMA1_10_X_MODIFY 0xFFC01E94
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#define DMA1_10_Y_MODIFY 0xFFC01E9C
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#define DMA1_10_CURR_DESC_PTR 0xFFC01EA0
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#define DMA1_10_CURR_ADDR 0xFFC01EA4
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#define DMA1_10_CURR_X_COUNT 0xFFC01EB0
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#define DMA1_10_CURR_Y_COUNT 0xFFC01EB8
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#define DMA1_10_IRQ_STATUS 0xFFC01EA8
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#define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC
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#define DMA1_11_CONFIG 0xFFC01EC8
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#define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0
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#define DMA1_11_START_ADDR 0xFFC01EC4
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#define DMA1_11_X_COUNT 0xFFC01ED0
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#define DMA1_11_Y_COUNT 0xFFC01ED8
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#define DMA1_11_X_MODIFY 0xFFC01ED4
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#define DMA1_11_Y_MODIFY 0xFFC01EDC
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#define DMA1_11_CURR_DESC_PTR 0xFFC01EE0
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#define DMA1_11_CURR_ADDR 0xFFC01EE4
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#define DMA1_11_CURR_X_COUNT 0xFFC01EF0
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#define DMA1_11_CURR_Y_COUNT 0xFFC01EF8
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#define DMA1_11_IRQ_STATUS 0xFFC01EE8
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#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC
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#define DMA2_TC_PER 0xFFC00B0C
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#define DMA2_TC_CNT 0xFFC01B10 /* Traffic Control Current Counts */
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#define DMA2_0_CONFIG 0xFFC00C08
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#define DMA2_0_NEXT_DESC_PTR 0xFFC00C00
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#define DMA2_0_START_ADDR 0xFFC00C04
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#define DMA2_0_X_COUNT 0xFFC00C10
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#define DMA2_0_Y_COUNT 0xFFC00C18
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#define DMA2_0_X_MODIFY 0xFFC00C14
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#define DMA2_0_Y_MODIFY 0xFFC00C1C
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#define DMA2_0_CURR_DESC_PTR 0xFFC00C20
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#define DMA2_0_CURR_ADDR 0xFFC00C24
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#define DMA2_0_CURR_X_COUNT 0xFFC00C30
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#define DMA2_0_CURR_Y_COUNT 0xFFC00C38
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#define DMA2_0_IRQ_STATUS 0xFFC00C28
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#define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C
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#define DMA2_1_CONFIG 0xFFC00C48
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#define DMA2_1_NEXT_DESC_PTR 0xFFC00C40
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#define DMA2_1_START_ADDR 0xFFC00C44
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#define DMA2_1_X_COUNT 0xFFC00C50
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#define DMA2_1_Y_COUNT 0xFFC00C58
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#define DMA2_1_X_MODIFY 0xFFC00C54
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#define DMA2_1_Y_MODIFY 0xFFC00C5C
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#define DMA2_1_CURR_DESC_PTR 0xFFC00C60
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#define DMA2_1_CURR_ADDR 0xFFC00C64
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#define DMA2_1_CURR_X_COUNT 0xFFC00C70
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#define DMA2_1_CURR_Y_COUNT 0xFFC00C78
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#define DMA2_1_IRQ_STATUS 0xFFC00C68
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#define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C
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#define DMA2_2_CONFIG 0xFFC00C88
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#define DMA2_2_NEXT_DESC_PTR 0xFFC00C80
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#define DMA2_2_START_ADDR 0xFFC00C84
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#define DMA2_2_X_COUNT 0xFFC00C90
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#define DMA2_2_Y_COUNT 0xFFC00C98
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#define DMA2_2_X_MODIFY 0xFFC00C94
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#define DMA2_2_Y_MODIFY 0xFFC00C9C
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#define DMA2_2_CURR_DESC_PTR 0xFFC00CA0
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#define DMA2_2_CURR_ADDR 0xFFC00CA4
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#define DMA2_2_CURR_X_COUNT 0xFFC00CB0
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#define DMA2_2_CURR_Y_COUNT 0xFFC00CB8
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#define DMA2_2_IRQ_STATUS 0xFFC00CA8
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#define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC
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#define DMA2_3_CONFIG 0xFFC00CC8
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#define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0
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#define DMA2_3_START_ADDR 0xFFC00CC4
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#define DMA2_3_X_COUNT 0xFFC00CD0
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#define DMA2_3_Y_COUNT 0xFFC00CD8
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#define DMA2_3_X_MODIFY 0xFFC00CD4
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#define DMA2_3_Y_MODIFY 0xFFC00CDC
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#define DMA2_3_CURR_DESC_PTR 0xFFC00CE0
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#define DMA2_3_CURR_ADDR 0xFFC00CE4
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#define DMA2_3_CURR_X_COUNT 0xFFC00CF0
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#define DMA2_3_CURR_Y_COUNT 0xFFC00CF8
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#define DMA2_3_IRQ_STATUS 0xFFC00CE8
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#define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC
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#define DMA2_4_CONFIG 0xFFC00D08
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#define DMA2_4_NEXT_DESC_PTR 0xFFC00D00
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#define DMA2_4_START_ADDR 0xFFC00D04
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#define DMA2_4_X_COUNT 0xFFC00D10
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#define DMA2_4_Y_COUNT 0xFFC00D18
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#define DMA2_4_X_MODIFY 0xFFC00D14
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#define DMA2_4_Y_MODIFY 0xFFC00D1C
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#define DMA2_4_CURR_DESC_PTR 0xFFC00D20
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#define DMA2_4_CURR_ADDR 0xFFC00D24
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#define DMA2_4_CURR_X_COUNT 0xFFC00D30
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#define DMA2_4_CURR_Y_COUNT 0xFFC00D38
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#define DMA2_4_IRQ_STATUS 0xFFC00D28
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#define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C
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#define DMA2_5_CONFIG 0xFFC00D48
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#define DMA2_5_NEXT_DESC_PTR 0xFFC00D40
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#define DMA2_5_START_ADDR 0xFFC00D44
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#define DMA2_5_X_COUNT 0xFFC00D50
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#define DMA2_5_Y_COUNT 0xFFC00D58
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#define DMA2_5_X_MODIFY 0xFFC00D54
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#define DMA2_5_Y_MODIFY 0xFFC00D5C
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#define DMA2_5_CURR_DESC_PTR 0xFFC00D60
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#define DMA2_5_CURR_ADDR 0xFFC00D64
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#define DMA2_5_CURR_X_COUNT 0xFFC00D70
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#define DMA2_5_CURR_Y_COUNT 0xFFC00D78
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#define DMA2_5_IRQ_STATUS 0xFFC00D68
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#define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C
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#define DMA2_6_CONFIG 0xFFC00D88
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#define DMA2_6_NEXT_DESC_PTR 0xFFC00D80
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#define DMA2_6_START_ADDR 0xFFC00D84
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#define DMA2_6_X_COUNT 0xFFC00D90
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#define DMA2_6_Y_COUNT 0xFFC00D98
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#define DMA2_6_X_MODIFY 0xFFC00D94
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#define DMA2_6_Y_MODIFY 0xFFC00D9C
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#define DMA2_6_CURR_DESC_PTR 0xFFC00DA0
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#define DMA2_6_CURR_ADDR 0xFFC00DA4
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#define DMA2_6_CURR_X_COUNT 0xFFC00DB0
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#define DMA2_6_CURR_Y_COUNT 0xFFC00DB8
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#define DMA2_6_IRQ_STATUS 0xFFC00DA8
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#define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC
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#define DMA2_7_CONFIG 0xFFC00DC8
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#define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0
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#define DMA2_7_START_ADDR 0xFFC00DC4
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#define DMA2_7_X_COUNT 0xFFC00DD0
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#define DMA2_7_Y_COUNT 0xFFC00DD8
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#define DMA2_7_X_MODIFY 0xFFC00DD4
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#define DMA2_7_Y_MODIFY 0xFFC00DDC
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#define DMA2_7_CURR_DESC_PTR 0xFFC00DE0
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#define DMA2_7_CURR_ADDR 0xFFC00DE4
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#define DMA2_7_CURR_X_COUNT 0xFFC00DF0
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#define DMA2_7_CURR_Y_COUNT 0xFFC00DF8
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#define DMA2_7_IRQ_STATUS 0xFFC00DE8
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#define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC
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#define DMA2_8_CONFIG 0xFFC00E08
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#define DMA2_8_NEXT_DESC_PTR 0xFFC00E00
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#define DMA2_8_START_ADDR 0xFFC00E04
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#define DMA2_8_X_COUNT 0xFFC00E10
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#define DMA2_8_Y_COUNT 0xFFC00E18
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#define DMA2_8_X_MODIFY 0xFFC00E14
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#define DMA2_8_Y_MODIFY 0xFFC00E1C
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#define DMA2_8_CURR_DESC_PTR 0xFFC00E20
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#define DMA2_8_CURR_ADDR 0xFFC00E24
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#define DMA2_8_CURR_X_COUNT 0xFFC00E30
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#define DMA2_8_CURR_Y_COUNT 0xFFC00E38
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#define DMA2_8_IRQ_STATUS 0xFFC00E28
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#define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C
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#define DMA2_9_CONFIG 0xFFC00E48
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#define DMA2_9_NEXT_DESC_PTR 0xFFC00E40
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#define DMA2_9_START_ADDR 0xFFC00E44
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#define DMA2_9_X_COUNT 0xFFC00E50
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#define DMA2_9_Y_COUNT 0xFFC00E58
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#define DMA2_9_X_MODIFY 0xFFC00E54
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#define DMA2_9_Y_MODIFY 0xFFC00E5C
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#define DMA2_9_CURR_DESC_PTR 0xFFC00E60
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#define DMA2_9_CURR_ADDR 0xFFC00E64
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#define DMA2_9_CURR_X_COUNT 0xFFC00E70
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#define DMA2_9_CURR_Y_COUNT 0xFFC00E78
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#define DMA2_9_IRQ_STATUS 0xFFC00E68
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#define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C
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#define DMA2_10_CONFIG 0xFFC00E88
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#define DMA2_10_NEXT_DESC_PTR 0xFFC00E80
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#define DMA2_10_START_ADDR 0xFFC00E84
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#define DMA2_10_X_COUNT 0xFFC00E90
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#define DMA2_10_Y_COUNT 0xFFC00E98
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#define DMA2_10_X_MODIFY 0xFFC00E94
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#define DMA2_10_Y_MODIFY 0xFFC00E9C
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#define DMA2_10_CURR_DESC_PTR 0xFFC00EA0
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#define DMA2_10_CURR_ADDR 0xFFC00EA4
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#define DMA2_10_CURR_X_COUNT 0xFFC00EB0
|
|
#define DMA2_10_CURR_Y_COUNT 0xFFC00EB8
|
|
#define DMA2_10_IRQ_STATUS 0xFFC00EA8
|
|
#define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC
|
|
#define DMA2_11_CONFIG 0xFFC00EC8
|
|
#define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0
|
|
#define DMA2_11_START_ADDR 0xFFC00EC4
|
|
#define DMA2_11_X_COUNT 0xFFC00ED0
|
|
#define DMA2_11_Y_COUNT 0xFFC00ED8
|
|
#define DMA2_11_X_MODIFY 0xFFC00ED4
|
|
#define DMA2_11_Y_MODIFY 0xFFC00EDC
|
|
#define DMA2_11_CURR_DESC_PTR 0xFFC00EE0
|
|
#define DMA2_11_CURR_ADDR 0xFFC00EE4
|
|
#define DMA2_11_CURR_X_COUNT 0xFFC00EF0
|
|
#define DMA2_11_CURR_Y_COUNT 0xFFC00EF8
|
|
#define DMA2_11_IRQ_STATUS 0xFFC00EE8
|
|
#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC
|
|
#define IMDMA_S0_CONFIG 0xFFC01848
|
|
#define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840
|
|
#define IMDMA_S0_START_ADDR 0xFFC01844
|
|
#define IMDMA_S0_X_COUNT 0xFFC01850
|
|
#define IMDMA_S0_Y_COUNT 0xFFC01858
|
|
#define IMDMA_S0_X_MODIFY 0xFFC01854
|
|
#define IMDMA_S0_Y_MODIFY 0xFFC0185C
|
|
#define IMDMA_S0_CURR_DESC_PTR 0xFFC01860
|
|
#define IMDMA_S0_CURR_ADDR 0xFFC01864
|
|
#define IMDMA_S0_CURR_X_COUNT 0xFFC01870
|
|
#define IMDMA_S0_CURR_Y_COUNT 0xFFC01878
|
|
#define IMDMA_S0_IRQ_STATUS 0xFFC01868
|
|
#define IMDMA_D0_CONFIG 0xFFC01808
|
|
#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800
|
|
#define IMDMA_D0_START_ADDR 0xFFC01804
|
|
#define IMDMA_D0_X_COUNT 0xFFC01810
|
|
#define IMDMA_D0_Y_COUNT 0xFFC01818
|
|
#define IMDMA_D0_X_MODIFY 0xFFC01814
|
|
#define IMDMA_D0_Y_MODIFY 0xFFC0181C
|
|
#define IMDMA_D0_CURR_DESC_PTR 0xFFC01820
|
|
#define IMDMA_D0_CURR_ADDR 0xFFC01824
|
|
#define IMDMA_D0_CURR_X_COUNT 0xFFC01830
|
|
#define IMDMA_D0_CURR_Y_COUNT 0xFFC01838
|
|
#define IMDMA_D0_IRQ_STATUS 0xFFC01828
|
|
#define IMDMA_S1_CONFIG 0xFFC018C8
|
|
#define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0
|
|
#define IMDMA_S1_START_ADDR 0xFFC018C4
|
|
#define IMDMA_S1_X_COUNT 0xFFC018D0
|
|
#define IMDMA_S1_Y_COUNT 0xFFC018D8
|
|
#define IMDMA_S1_X_MODIFY 0xFFC018D4
|
|
#define IMDMA_S1_Y_MODIFY 0xFFC018DC
|
|
#define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0
|
|
#define IMDMA_S1_CURR_ADDR 0xFFC018E4
|
|
#define IMDMA_S1_CURR_X_COUNT 0xFFC018F0
|
|
#define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8
|
|
#define IMDMA_S1_IRQ_STATUS 0xFFC018E8
|
|
#define IMDMA_D1_CONFIG 0xFFC01888
|
|
#define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880
|
|
#define IMDMA_D1_START_ADDR 0xFFC01884
|
|
#define IMDMA_D1_X_COUNT 0xFFC01890
|
|
#define IMDMA_D1_Y_COUNT 0xFFC01898
|
|
#define IMDMA_D1_X_MODIFY 0xFFC01894
|
|
#define IMDMA_D1_Y_MODIFY 0xFFC0189C
|
|
#define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0
|
|
#define IMDMA_D1_CURR_ADDR 0xFFC018A4
|
|
#define IMDMA_D1_CURR_X_COUNT 0xFFC018B0
|
|
#define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8
|
|
#define IMDMA_D1_IRQ_STATUS 0xFFC018A8
|
|
#define MDMA1_S0_CONFIG 0xFFC01F48
|
|
#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40
|
|
#define MDMA1_S0_START_ADDR 0xFFC01F44
|
|
#define MDMA1_S0_X_COUNT 0xFFC01F50
|
|
#define MDMA1_S0_Y_COUNT 0xFFC01F58
|
|
#define MDMA1_S0_X_MODIFY 0xFFC01F54
|
|
#define MDMA1_S0_Y_MODIFY 0xFFC01F5C
|
|
#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60
|
|
#define MDMA1_S0_CURR_ADDR 0xFFC01F64
|
|
#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70
|
|
#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78
|
|
#define MDMA1_S0_IRQ_STATUS 0xFFC01F68
|
|
#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C
|
|
#define MDMA1_D0_CONFIG 0xFFC01F08
|
|
#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00
|
|
#define MDMA1_D0_START_ADDR 0xFFC01F04
|
|
#define MDMA1_D0_X_COUNT 0xFFC01F10
|
|
#define MDMA1_D0_Y_COUNT 0xFFC01F18
|
|
#define MDMA1_D0_X_MODIFY 0xFFC01F14
|
|
#define MDMA1_D0_Y_MODIFY 0xFFC01F1C
|
|
#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20
|
|
#define MDMA1_D0_CURR_ADDR 0xFFC01F24
|
|
#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30
|
|
#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38
|
|
#define MDMA1_D0_IRQ_STATUS 0xFFC01F28
|
|
#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C
|
|
#define MDMA1_S1_CONFIG 0xFFC01FC8
|
|
#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0
|
|
#define MDMA1_S1_START_ADDR 0xFFC01FC4
|
|
#define MDMA1_S1_X_COUNT 0xFFC01FD0
|
|
#define MDMA1_S1_Y_COUNT 0xFFC01FD8
|
|
#define MDMA1_S1_X_MODIFY 0xFFC01FD4
|
|
#define MDMA1_S1_Y_MODIFY 0xFFC01FDC
|
|
#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0
|
|
#define MDMA1_S1_CURR_ADDR 0xFFC01FE4
|
|
#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0
|
|
#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8
|
|
#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8
|
|
#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC
|
|
#define MDMA1_D1_CONFIG 0xFFC01F88
|
|
#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80
|
|
#define MDMA1_D1_START_ADDR 0xFFC01F84
|
|
#define MDMA1_D1_X_COUNT 0xFFC01F90
|
|
#define MDMA1_D1_Y_COUNT 0xFFC01F98
|
|
#define MDMA1_D1_X_MODIFY 0xFFC01F94
|
|
#define MDMA1_D1_Y_MODIFY 0xFFC01F9C
|
|
#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0
|
|
#define MDMA1_D1_CURR_ADDR 0xFFC01FA4
|
|
#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0
|
|
#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8
|
|
#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8
|
|
#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC
|
|
#define MDMA2_S0_CONFIG 0xFFC00F48
|
|
#define MDMA2_S0_NEXT_DESC_PTR 0xFFC00F40
|
|
#define MDMA2_S0_START_ADDR 0xFFC00F44
|
|
#define MDMA2_S0_X_COUNT 0xFFC00F50
|
|
#define MDMA2_S0_Y_COUNT 0xFFC00F58
|
|
#define MDMA2_S0_X_MODIFY 0xFFC00F54
|
|
#define MDMA2_S0_Y_MODIFY 0xFFC00F5C
|
|
#define MDMA2_S0_CURR_DESC_PTR 0xFFC00F60
|
|
#define MDMA2_S0_CURR_ADDR 0xFFC00F64
|
|
#define MDMA2_S0_CURR_X_COUNT 0xFFC00F70
|
|
#define MDMA2_S0_CURR_Y_COUNT 0xFFC00F78
|
|
#define MDMA2_S0_IRQ_STATUS 0xFFC00F68
|
|
#define MDMA2_S0_PERIPHERAL_MAP 0xFFC00F6C
|
|
#define MDMA2_D0_CONFIG 0xFFC00F08
|
|
#define MDMA2_D0_NEXT_DESC_PTR 0xFFC00F00
|
|
#define MDMA2_D0_START_ADDR 0xFFC00F04
|
|
#define MDMA2_D0_X_COUNT 0xFFC00F10
|
|
#define MDMA2_D0_Y_COUNT 0xFFC00F18
|
|
#define MDMA2_D0_X_MODIFY 0xFFC00F14
|
|
#define MDMA2_D0_Y_MODIFY 0xFFC00F1C
|
|
#define MDMA2_D0_CURR_DESC_PTR 0xFFC00F20
|
|
#define MDMA2_D0_CURR_ADDR 0xFFC00F24
|
|
#define MDMA2_D0_CURR_X_COUNT 0xFFC00F30
|
|
#define MDMA2_D0_CURR_Y_COUNT 0xFFC00F38
|
|
#define MDMA2_D0_IRQ_STATUS 0xFFC00F28
|
|
#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C
|
|
#define MDMA2_S1_CONFIG 0xFFC00FC8
|
|
#define MDMA2_S1_NEXT_DESC_PTR 0xFFC00FC0
|
|
#define MDMA2_S1_START_ADDR 0xFFC00FC4
|
|
#define MDMA2_S1_X_COUNT 0xFFC00FD0
|
|
#define MDMA2_S1_Y_COUNT 0xFFC00FD8
|
|
#define MDMA2_S1_X_MODIFY 0xFFC00FD4
|
|
#define MDMA2_S1_Y_MODIFY 0xFFC00FDC
|
|
#define MDMA2_S1_CURR_DESC_PTR 0xFFC00FE0
|
|
#define MDMA2_S1_CURR_ADDR 0xFFC00FE4
|
|
#define MDMA2_S1_CURR_X_COUNT 0xFFC00FF0
|
|
#define MDMA2_S1_CURR_Y_COUNT 0xFFC00FF8
|
|
#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8
|
|
#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC
|
|
#define MDMA2_D1_CONFIG 0xFFC00F88
|
|
#define MDMA2_D1_NEXT_DESC_PTR 0xFFC00F80
|
|
#define MDMA2_D1_START_ADDR 0xFFC00F84
|
|
#define MDMA2_D1_X_COUNT 0xFFC00F90
|
|
#define MDMA2_D1_Y_COUNT 0xFFC00F98
|
|
#define MDMA2_D1_X_MODIFY 0xFFC00F94
|
|
#define MDMA2_D1_Y_MODIFY 0xFFC00F9C
|
|
#define MDMA2_D1_CURR_DESC_PTR 0xFFC00FA0
|
|
#define MDMA2_D1_CURR_ADDR 0xFFC00FA4
|
|
#define MDMA2_D1_CURR_X_COUNT 0xFFC00FB0
|
|
#define MDMA2_D1_CURR_Y_COUNT 0xFFC00FB8
|
|
#define MDMA2_D1_IRQ_STATUS 0xFFC00FA8
|
|
#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC
|
|
#define TIMER0_CONFIG 0xFFC00600
|
|
#define TIMER0_COUNTER 0xFFC00604
|
|
#define TIMER0_PERIOD 0xFFC00608
|
|
#define TIMER0_WIDTH 0xFFC0060C
|
|
#define TIMER1_CONFIG 0xFFC00610
|
|
#define TIMER1_COUNTER 0xFFC00614
|
|
#define TIMER1_PERIOD 0xFFC00618
|
|
#define TIMER1_WIDTH 0xFFC0061C
|
|
#define TIMER2_CONFIG 0xFFC00620
|
|
#define TIMER2_COUNTER 0xFFC00624
|
|
#define TIMER2_PERIOD 0xFFC00628
|
|
#define TIMER2_WIDTH 0xFFC0062C
|
|
#define TIMER3_CONFIG 0xFFC00630
|
|
#define TIMER3_COUNTER 0xFFC00634
|
|
#define TIMER3_PERIOD 0xFFC00638
|
|
#define TIMER3_WIDTH 0xFFC0063C
|
|
#define TIMER4_CONFIG 0xFFC00640
|
|
#define TIMER4_COUNTER 0xFFC00644
|
|
#define TIMER4_PERIOD 0xFFC00648
|
|
#define TIMER4_WIDTH 0xFFC0064C
|
|
#define TIMER5_CONFIG 0xFFC00650
|
|
#define TIMER5_COUNTER 0xFFC00654
|
|
#define TIMER5_PERIOD 0xFFC00658
|
|
#define TIMER5_WIDTH 0xFFC0065C
|
|
#define TIMER6_CONFIG 0xFFC00660
|
|
#define TIMER6_COUNTER 0xFFC00664
|
|
#define TIMER6_PERIOD 0xFFC00668
|
|
#define TIMER6_WIDTH 0xFFC0066C
|
|
#define TIMER7_CONFIG 0xFFC00670
|
|
#define TIMER7_COUNTER 0xFFC00674
|
|
#define TIMER7_PERIOD 0xFFC00678
|
|
#define TIMER7_WIDTH 0xFFC0067C
|
|
#define TIMER8_CONFIG 0xFFC01600
|
|
#define TIMER8_COUNTER 0xFFC01604
|
|
#define TIMER8_PERIOD 0xFFC01608
|
|
#define TIMER8_WIDTH 0xFFC0160C
|
|
#define TIMER9_CONFIG 0xFFC01610
|
|
#define TIMER9_COUNTER 0xFFC01614
|
|
#define TIMER9_PERIOD 0xFFC01618
|
|
#define TIMER9_WIDTH 0xFFC0161C
|
|
#define TIMER10_CONFIG 0xFFC01620
|
|
#define TIMER10_COUNTER 0xFFC01624
|
|
#define TIMER10_PERIOD 0xFFC01628
|
|
#define TIMER10_WIDTH 0xFFC0162C
|
|
#define TIMER11_CONFIG 0xFFC01630
|
|
#define TIMER11_COUNTER 0xFFC01634
|
|
#define TIMER11_PERIOD 0xFFC01638
|
|
#define TIMER11_WIDTH 0xFFC0163C
|
|
#define TMRS4_ENABLE 0xFFC01640
|
|
#define TMRS4_DISABLE 0xFFC01644
|
|
#define TMRS4_STATUS 0xFFC01648
|
|
#define TMRS8_ENABLE 0xFFC00680
|
|
#define TMRS8_DISABLE 0xFFC00684
|
|
#define TMRS8_STATUS 0xFFC00688
|
|
#define FIO0_FLAG_D 0xFFC00700
|
|
#define FIO0_FLAG_C 0xFFC00704
|
|
#define FIO0_FLAG_S 0xFFC00708
|
|
#define FIO0_FLAG_T 0xFFC0070C
|
|
#define FIO0_MASKA_D 0xFFC00710
|
|
#define FIO0_MASKA_C 0xFFC00714
|
|
#define FIO0_MASKA_S 0xFFC00718
|
|
#define FIO0_MASKA_T 0xFFC0071C
|
|
#define FIO0_MASKB_D 0xFFC00720
|
|
#define FIO0_MASKB_C 0xFFC00724
|
|
#define FIO0_MASKB_S 0xFFC00728
|
|
#define FIO0_MASKB_T 0xFFC0072C
|
|
#define FIO0_DIR 0xFFC00730
|
|
#define FIO0_POLAR 0xFFC00734
|
|
#define FIO0_EDGE 0xFFC00738
|
|
#define FIO0_BOTH 0xFFC0073C
|
|
#define FIO0_INEN 0xFFC00740
|
|
#define FIO1_FLAG_D 0xFFC01500
|
|
#define FIO1_FLAG_C 0xFFC01504
|
|
#define FIO1_FLAG_S 0xFFC01508
|
|
#define FIO1_FLAG_T 0xFFC0150C
|
|
#define FIO1_MASKA_D 0xFFC01510
|
|
#define FIO1_MASKA_C 0xFFC01514
|
|
#define FIO1_MASKA_S 0xFFC01518
|
|
#define FIO1_MASKA_T 0xFFC0151C
|
|
#define FIO1_MASKB_D 0xFFC01520
|
|
#define FIO1_MASKB_C 0xFFC01524
|
|
#define FIO1_MASKB_S 0xFFC01528
|
|
#define FIO1_MASKB_T 0xFFC0152C
|
|
#define FIO1_DIR 0xFFC01530
|
|
#define FIO1_POLAR 0xFFC01534
|
|
#define FIO1_EDGE 0xFFC01538
|
|
#define FIO1_BOTH 0xFFC0153C
|
|
#define FIO1_INEN 0xFFC01540
|
|
#define FIO2_FLAG_D 0xFFC01700
|
|
#define FIO2_FLAG_C 0xFFC01704
|
|
#define FIO2_FLAG_S 0xFFC01708
|
|
#define FIO2_FLAG_T 0xFFC0170C
|
|
#define FIO2_MASKA_D 0xFFC01710
|
|
#define FIO2_MASKA_C 0xFFC01714
|
|
#define FIO2_MASKA_S 0xFFC01718
|
|
#define FIO2_MASKA_T 0xFFC0171C
|
|
#define FIO2_MASKB_D 0xFFC01720
|
|
#define FIO2_MASKB_C 0xFFC01724
|
|
#define FIO2_MASKB_S 0xFFC01728
|
|
#define FIO2_MASKB_T 0xFFC0172C
|
|
#define FIO2_DIR 0xFFC01730
|
|
#define FIO2_POLAR 0xFFC01734
|
|
#define FIO2_EDGE 0xFFC01738
|
|
#define FIO2_BOTH 0xFFC0173C
|
|
#define FIO2_INEN 0xFFC01740
|
|
#define SPORT0_TCR1 0xFFC00800
|
|
#define SPORT0_TCR2 0xFFC00804
|
|
#define SPORT0_TCLKDIV 0xFFC00808
|
|
#define SPORT0_TFSDIV 0xFFC0080C
|
|
#define SPORT0_TX 0xFFC00810
|
|
#define SPORT0_RX 0xFFC00818
|
|
#define SPORT0_RCR1 0xFFC00820
|
|
#define SPORT0_RCR2 0xFFC00824
|
|
#define SPORT0_RCLKDIV 0xFFC00828
|
|
#define SPORT0_RFSDIV 0xFFC0082C
|
|
#define SPORT0_STAT 0xFFC00830
|
|
#define SPORT0_CHNL 0xFFC00834
|
|
#define SPORT0_MCMC1 0xFFC00838
|
|
#define SPORT0_MCMC2 0xFFC0083C
|
|
#define SPORT0_MTCS0 0xFFC00840
|
|
#define SPORT0_MTCS1 0xFFC00844
|
|
#define SPORT0_MTCS2 0xFFC00848
|
|
#define SPORT0_MTCS3 0xFFC0084C
|
|
#define SPORT0_MRCS0 0xFFC00850
|
|
#define SPORT0_MRCS1 0xFFC00854
|
|
#define SPORT0_MRCS2 0xFFC00858
|
|
#define SPORT0_MRCS3 0xFFC0085C
|
|
#define SPORT1_TCR1 0xFFC00900
|
|
#define SPORT1_TCR2 0xFFC00904
|
|
#define SPORT1_TCLKDIV 0xFFC00908
|
|
#define SPORT1_TFSDIV 0xFFC0090C
|
|
#define SPORT1_TX 0xFFC00910
|
|
#define SPORT1_RX 0xFFC00918
|
|
#define SPORT1_RCR1 0xFFC00920
|
|
#define SPORT1_RCR2 0xFFC00924
|
|
#define SPORT1_RCLKDIV 0xFFC00928
|
|
#define SPORT1_RFSDIV 0xFFC0092C
|
|
#define SPORT1_STAT 0xFFC00930
|
|
#define SPORT1_CHNL 0xFFC00934
|
|
#define SPORT1_MCMC1 0xFFC00938
|
|
#define SPORT1_MCMC2 0xFFC0093C
|
|
#define SPORT1_MTCS0 0xFFC00940
|
|
#define SPORT1_MTCS1 0xFFC00944
|
|
#define SPORT1_MTCS2 0xFFC00948
|
|
#define SPORT1_MTCS3 0xFFC0094C
|
|
#define SPORT1_MRCS0 0xFFC00950
|
|
#define SPORT1_MRCS1 0xFFC00954
|
|
#define SPORT1_MRCS2 0xFFC00958
|
|
#define SPORT1_MRCS3 0xFFC0095C
|
|
#define SICA_SWRST 0xFFC00100
|
|
#define SICA_SYSCR 0xFFC00104
|
|
#define SICA_RVECT 0xFFC00108
|
|
#define SICA_IMASK0 0xFFC0010C
|
|
#define SICA_IMASK1 0xFFC00110
|
|
#define SICA_ISR0 0xFFC00114
|
|
#define SICA_ISR1 0xFFC00118
|
|
#define SICA_IWR0 0xFFC0011C
|
|
#define SICA_IWR1 0xFFC00120
|
|
#define SICA_IAR0 0xFFC00124
|
|
#define SICA_IAR1 0xFFC00128
|
|
#define SICA_IAR2 0xFFC0012C
|
|
#define SICA_IAR3 0xFFC00130
|
|
#define SICA_IAR4 0xFFC00134
|
|
#define SICA_IAR5 0xFFC00138
|
|
#define SICA_IAR6 0xFFC0013C
|
|
#define SICA_IAR7 0xFFC00140
|
|
#define SICB_SWRST 0xFFC01100
|
|
#define SICB_SYSCR 0xFFC01104
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#define SICB_RVECT 0xFFC01108
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#define SICB_IMASK0 0xFFC0110C
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#define SICB_IMASK1 0xFFC01110
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#define SICB_ISR0 0xFFC01114
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#define SICB_ISR1 0xFFC01118
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#define SICB_IWR0 0xFFC0111C
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#define SICB_IWR1 0xFFC01120
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#define SICB_IAR0 0xFFC01124
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#define SICB_IAR1 0xFFC01128
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#define SICB_IAR2 0xFFC0112C
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#define SICB_IAR3 0xFFC01130
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#define SICB_IAR4 0xFFC01134
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#define SICB_IAR5 0xFFC01138
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#define SICB_IAR6 0xFFC0113C
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#define SICB_IAR7 0xFFC01140
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#define PPI0_CONTROL 0xFFC01000
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#define PPI0_STATUS 0xFFC01004
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#define PPI0_DELAY 0xFFC0100C
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#define PPI0_COUNT 0xFFC01008
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#define PPI0_FRAME 0xFFC01010
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#define PPI1_CONTROL 0xFFC01300
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#define PPI1_STATUS 0xFFC01304
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#define PPI1_DELAY 0xFFC0130C
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#define PPI1_COUNT 0xFFC01308
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#define PPI1_FRAME 0xFFC01310
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#define UART_THR 0xFFC00400
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#define UART_RBR 0xFFC00400
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#define UART_DLL 0xFFC00400
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#define UART_DLH 0xFFC00404
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#define UART_IER 0xFFC00404
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#define UART_IIR 0xFFC00408
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#define UART_LCR 0xFFC0040C
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#define UART_MCR 0xFFC00410
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#define UART_LSR 0xFFC00414
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#define UART_MSR 0xFFC00418
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#define UART_SCR 0xFFC0041C
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#define UART_GCTL 0xFFC00424
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#define UART_GBL 0xFFC00424
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#define EBIU_AMGCTL 0xFFC00A00
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#define EBIU_AMBCTL0 0xFFC00A04
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#define EBIU_AMBCTL1 0xFFC00A08
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#define EBIU_SDGCTL 0xFFC00A10
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#define EBIU_SDBCTL 0xFFC00A14
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#define EBIU_SDRRC 0xFFC00A18
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#define EBIU_SDSTAT 0xFFC00A1C
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#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA03FFF Instruction Bank A SRAM */
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#define L1_INST_SRAM_SIZE (0xFFA03FFF - 0xFFA00000 + 1)
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#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
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#endif /* __BFIN_DEF_ADSP_BF561_proc__ */
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