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24985686fe
The current imx8mp-dhcom-som.dtsi describes production rev.200 SoM, add DT overlay which reinstates rev.100 SoM description to permit prototype rev.100 SoMs to be used until they get phased out. Signed-off-by: Marek Vasut <marex@denx.de>
247 lines
6.3 KiB
C
247 lines
6.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2022 Marek Vasut <marex@denx.de>
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*/
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#include <common.h>
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#include <hang.h>
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#include <image.h>
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#include <init.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm-generic/gpio.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx8mp_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/arch/ddr.h>
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#include <asm/sections.h>
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#include <dm/uclass.h>
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#include <dm/device.h>
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#include <dm/uclass-internal.h>
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#include <dm/device-internal.h>
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#include <linux/bitfield.h>
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#include <power/pmic.h>
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#include <power/pca9450.h>
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#include "lpddr4_timing.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
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#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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static const iomux_v3_cfg_t uart_pads[] = {
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MX8MP_PAD_SAI2_RXFS__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX8MP_PAD_SAI2_RXC__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static const iomux_v3_cfg_t wdog_pads[] = {
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MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
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};
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static bool dh_gigabit_eqos, dh_gigabit_fec;
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static u8 dh_som_rev;
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static void dh_imx8mp_early_init_f(void)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
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imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
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set_wdog_reset(wdog);
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
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}
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static int dh_imx8mp_board_power_init(void)
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{
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struct udevice *dev;
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int ret;
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ret = pmic_get("pmic@25", &dev);
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if (ret == -ENODEV) {
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puts("Failed to get PMIC\n");
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return 0;
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}
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if (ret != 0)
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return ret;
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/* BUCKxOUT_DVS0/1 control BUCK123 output. */
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pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
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/* Increase VDD_SOC to typical value 0.95V before first DRAM access. */
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if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV))
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/* Set DVS0 to 0.85V for special case. */
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pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
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else
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pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1c);
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/* Set DVS1 to 0.85v for suspend. */
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pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
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/*
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* Enable DVS control through PMIC_STBY_REQ and
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* set B1_ENMODE=1 (ON by PMIC_ON_REQ=H).
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*/
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pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
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/* Kernel uses OD/OD frequency for SoC. */
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/* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95V */
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pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c);
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/* Set LDO4 and CONFIG2 to enable the I2C level translator. */
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pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59);
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pmic_reg_write(dev, PCA9450_CONFIG2, 0x1);
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return 0;
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}
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static struct dram_timing_info *dram_timing_info[8] = {
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NULL, /* 512 MiB */
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NULL, /* 1024 MiB */
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NULL, /* 1536 MiB */
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&dh_imx8mp_dhcom_dram_timing_16g_x32, /* 2048 MiB */
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NULL, /* 3072 MiB */
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&dh_imx8mp_dhcom_dram_timing_32g_x32, /* 4096 MiB */
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NULL, /* 6144 MiB */
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NULL, /* 8192 MiB */
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};
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static void spl_dram_init(void)
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{
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const u16 size[] = { 512, 1024, 1536, 2048, 3072, 4096, 6144, 8192 };
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u8 memcfg = dh_get_memcfg();
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int i;
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printf("DDR: %d MiB [0x%x]\n", size[memcfg], memcfg);
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if (!dram_timing_info[memcfg]) {
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printf("Unsupported DRAM strapping, trying lowest supported. MEMCFG=0x%x\n",
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memcfg);
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for (i = 0; i < ARRAY_SIZE(dram_timing_info); i++)
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if (dram_timing_info[i]) /* Configuration found */
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break;
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}
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ddr_init(dram_timing_info[memcfg]);
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}
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void spl_board_init(void)
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{
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/*
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* Set GIC clock to 500 MHz for OD VDD_SOC. Kernel driver does not
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* allow to change it. Should set the clock after PMIC setting done.
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* Default is 400 MHz (system_pll1_800m with div = 2) set by ROM for
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* ND VDD_SOC.
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*/
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clock_enable(CCGR_GIC, 0);
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clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
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clock_enable(CCGR_GIC, 1);
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}
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int spl_board_boot_device(enum boot_device boot_dev_spl)
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{
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return BOOT_DEVICE_BOOTROM;
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}
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int board_spl_fit_append_fdt_skip(const char *name)
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{
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if (!dh_gigabit_eqos) { /* 1x or 2x RMII PHY SoM */
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if (dh_gigabit_fec) { /* 1x RMII PHY SoM */
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if (!strcmp(name, "fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast"))
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return 0;
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} else { /* 2x RMII PHY SoM */
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if (!strcmp(name, "fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast"))
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return 0;
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if (!strcmp(name, "fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast")) {
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/* 2x RMII PHY SoM on PDK2 or PDK3 */
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if (of_machine_is_compatible("dh,imx8mp-dhcom-pdk2") ||
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of_machine_is_compatible("dh,imx8mp-dhcom-pdk3"))
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return 0;
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}
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}
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}
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if (dh_som_rev == 0x0) { /* Prototype SoM rev.100 */
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if (!strcmp(name, "fdt-dto-imx8mp-dhcom-som-overlay-rev100"))
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return 0;
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if (!strcmp(name, "fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100") &&
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of_machine_is_compatible("dh,imx8mp-dhcom-pdk3"))
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return 0;
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}
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return 1; /* Skip this DTO */
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}
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static void dh_imx8mp_board_cache_config(void)
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{
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const void __iomem *mux_base = (void __iomem *)IOMUXC_BASE_ADDR;
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const u32 mux_sion[] = {
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FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_ENET_RX_CTL__GPIO1_IO24),
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FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_SAI1_TXFS__GPIO4_IO10),
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FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_NAND_DQS__GPIO3_IO14),
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FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_SAI1_TXD7__GPIO4_IO19),
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FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_SAI5_MCLK__GPIO3_IO25),
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};
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int i;
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for (i = 0; i < ARRAY_SIZE(mux_sion); i++)
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setbits_le32(mux_base + mux_sion[i], IOMUX_CONFIG_SION);
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dh_gigabit_eqos = !(readl(GPIO1_BASE_ADDR) & BIT(24));
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dh_gigabit_fec = !(readl(GPIO4_BASE_ADDR) & BIT(10));
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dh_som_rev = !!(readl(GPIO3_BASE_ADDR) & BIT(14));
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dh_som_rev |= !!(readl(GPIO4_BASE_ADDR) & BIT(19)) << 1;
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dh_som_rev |= !!(readl(GPIO3_BASE_ADDR) & BIT(25)) << 2;
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for (i = 0; i < ARRAY_SIZE(mux_sion); i++)
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clrbits_le32(mux_base + mux_sion[i], IOMUX_CONFIG_SION);
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}
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void board_init_f(ulong dummy)
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{
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struct udevice *dev;
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int ret;
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arch_cpu_init();
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init_uart_clk(0);
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dh_imx8mp_early_init_f();
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preloader_console_init();
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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ret = spl_early_init();
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if (ret) {
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debug("spl_early_init() failed: %d\n", ret);
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hang();
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}
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ret = uclass_get_device_by_name(UCLASS_CLK,
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"clock-controller@30380000",
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&dev);
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if (ret < 0) {
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printf("Failed to find clock node. Check device tree\n");
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hang();
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}
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enable_tzc380();
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dh_imx8mp_board_power_init();
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/* DDR initialization */
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spl_dram_init();
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dh_imx8mp_board_cache_config();
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board_init_r(NULL, 0);
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}
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