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83c484d7ec
Add the Silicon Image series PCI Express to Serial ATA controller support, including Sil3132, Sil3131 and Sil3124. The SATA controller can be used to load kernel. The features list: - Supports 1-lane 2.5 Gbit/s PCI Express - Supports one/two/four independent Serial ATA channels - Supports Serial ATA Generation 2 transfer rate of 3.0 Gbit/s - Supports LBA28 and LBA48 Signed-off-by: Tang Yuantian <b29983@freescale.com> Signed-off-by: Aaron Williams <Aaron.Williams@cavium.com> Tested-by: Lan Chunhe <b25806@freescale.com>
229 lines
7 KiB
C
229 lines
7 KiB
C
/*
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* Copyright (C) 2011 Freescale Semiconductor, Inc.
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* Author: Tang Yuantian <b29983@freescale.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef SATA_SIL3132_H
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#define SATA_SIL3132_H
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#define READ_CMD 0
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#define WRITE_CMD 1
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extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
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/*
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* SATA device driver struct for each dev
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*/
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struct sil_sata {
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char name[12];
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void *port; /* the port base address */
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int lba48;
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u16 pio;
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u16 mwdma;
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u16 udma;
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pci_dev_t devno;
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int wcache;
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int flush;
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int flush_ext;
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};
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/* sata info for each controller */
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struct sata_info {
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ulong iobase[3];
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pci_dev_t devno;
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int portbase;
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int maxport;
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};
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/*
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* Scatter gather entry (SGE),MUST 8 bytes aligned
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*/
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struct sil_sge {
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__le64 addr;
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__le32 cnt;
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__le32 flags;
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} __attribute__ ((aligned(8), packed));
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/*
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* Port request block, MUST 8 bytes aligned
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*/
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struct sil_prb {
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__le16 ctrl;
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__le16 prot;
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__le32 rx_cnt;
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struct sata_fis_h2d fis;
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} __attribute__ ((aligned(8), packed));
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struct sil_cmd_block {
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struct sil_prb prb;
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struct sil_sge sge;
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};
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enum {
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HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
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HOST_CTRL = 0x40,
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HOST_IRQ_STAT = 0x44,
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HOST_PHY_CFG = 0x48,
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HOST_BIST_CTRL = 0x50,
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HOST_BIST_PTRN = 0x54,
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HOST_BIST_STAT = 0x58,
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HOST_MEM_BIST_STAT = 0x5c,
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HOST_FLASH_CMD = 0x70,
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/* 8 bit regs */
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HOST_FLASH_DATA = 0x74,
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HOST_TRANSITION_DETECT = 0x75,
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HOST_GPIO_CTRL = 0x76,
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HOST_I2C_ADDR = 0x78, /* 32 bit */
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HOST_I2C_DATA = 0x7c,
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HOST_I2C_XFER_CNT = 0x7e,
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HOST_I2C_CTRL = 0x7f,
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/* HOST_SLOT_STAT bits */
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HOST_SSTAT_ATTN = (1 << 31),
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/* HOST_CTRL bits */
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HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
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HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
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HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
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HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
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HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
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HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
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/*
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* Port registers
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* (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
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*/
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PORT_REGS_SIZE = 0x2000,
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PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
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PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
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PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
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PORT_PMP_STATUS = 0x0000, /* port device status offset */
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PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
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PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
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/* 32 bit regs */
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PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
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PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
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PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
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PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
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PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
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PORT_ACTIVATE_UPPER_ADDR = 0x101c,
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PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
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PORT_CMD_ERR = 0x1024, /* command error number */
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PORT_FIS_CFG = 0x1028,
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PORT_FIFO_THRES = 0x102c,
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/* 16 bit regs */
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PORT_DECODE_ERR_CNT = 0x1040,
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PORT_DECODE_ERR_THRESH = 0x1042,
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PORT_CRC_ERR_CNT = 0x1044,
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PORT_CRC_ERR_THRESH = 0x1046,
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PORT_HSHK_ERR_CNT = 0x1048,
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PORT_HSHK_ERR_THRESH = 0x104a,
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/* 32 bit regs */
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PORT_PHY_CFG = 0x1050,
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PORT_SLOT_STAT = 0x1800,
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PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 */
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PORT_CONTEXT = 0x1e04,
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PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 */
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PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 */
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PORT_SCONTROL = 0x1f00,
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PORT_SSTATUS = 0x1f04,
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PORT_SERROR = 0x1f08,
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PORT_SACTIVE = 0x1f0c,
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/* PORT_CTRL_STAT bits */
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PORT_CS_PORT_RST = (1 << 0), /* port reset */
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PORT_CS_DEV_RST = (1 << 1), /* device reset */
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PORT_CS_INIT = (1 << 2), /* port initialize */
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PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
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PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
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PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
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PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
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PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
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PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
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/* PORT_IRQ_STAT/ENABLE_SET/CLR */
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/* bits[11:0] are masked */
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PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
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PORT_IRQ_ERROR = (1 << 1), /* command execution error */
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PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
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PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
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PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
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PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
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PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
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PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
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PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
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PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
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PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
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PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
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DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
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PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
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PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
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/* bits[27:16] are unmasked (raw) */
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PORT_IRQ_RAW_SHIFT = 16,
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PORT_IRQ_MASKED_MASK = 0x7ff,
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PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
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/* ENABLE_SET/CLR specific, intr steering - 2 bit field */
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PORT_IRQ_STEER_SHIFT = 30,
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PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
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/* PORT_CMD_ERR constants */
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PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
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PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
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PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
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PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
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PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
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PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
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PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
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PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
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/* bits of PRB control field */
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PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
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PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
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PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
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PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
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PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
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/* PRB protocol field */
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PRB_PROT_PACKET = (1 << 0),
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PRB_PROT_TCQ = (1 << 1),
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PRB_PROT_NCQ = (1 << 2),
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PRB_PROT_READ = (1 << 3),
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PRB_PROT_WRITE = (1 << 4),
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PRB_PROT_TRANSPARENT = (1 << 5),
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/*
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* Other constants
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*/
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SGE_TRM = (1 << 31), /* Last SGE in chain */
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SGE_LNK = (1 << 30), /* linked list
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Points to SGT, not SGE */
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SGE_DRD = (1 << 29), /* discard data read (/dev/null)
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data address ignored */
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CMD_ERR = 0x21,
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};
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#endif
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