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https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
275 lines
8.3 KiB
C
275 lines
8.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
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*
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* Copyright (C) 2006 Micronas GmbH
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*/
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#include <common.h>
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#include "vct.h"
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typedef union _TOP_PINMUX_t
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{
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u32 reg;
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struct {
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u32 res : 24; /* reserved */
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u32 drive : 2; /* Driver strength */
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u32 slew : 1; /* Slew rate */
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u32 strig : 1; /* Schmitt trigger input*/
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u32 pu_pd : 2; /* Pull up/ pull down */
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u32 funsel : 2; /* Pin function */
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} Bits;
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} TOP_PINMUX_t;
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#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
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static TOP_PINMUX_t top_read_pin(int pin)
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{
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TOP_PINMUX_t reg;
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switch (pin) {
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case 2:
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case 3:
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case 6:
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case 9:
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reg.reg = 0xdeadbeef;
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break;
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case 4:
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reg.reg = reg_read(FWSRAM_TOP_SCL_CFG(FWSRAM_BASE));
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break;
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case 5:
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reg.reg = reg_read(FWSRAM_TOP_SDA_CFG(FWSRAM_BASE));
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break;
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case 7:
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reg.reg = reg_read(FWSRAM_TOP_TDO_CFG(FWSRAM_BASE));
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break;
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case 8:
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reg.reg = reg_read(FWSRAM_TOP_GPIO2_0_CFG(FWSRAM_BASE));
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break;
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case 10:
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case 11:
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case 12:
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case 13:
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case 14:
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case 15:
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case 16:
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reg.reg = reg_read(FWSRAM_BASE + FWSRAM_TOP_GPIO2_1_CFG_OFFS +
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((pin - 10) * 4));
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break;
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default:
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reg.reg = reg_read(TOP_BASE + (pin * 4));
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break;
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}
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return reg;
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}
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static void top_write_pin(int pin, TOP_PINMUX_t reg)
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{
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switch (pin) {
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case 4:
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reg_write(FWSRAM_TOP_SCL_CFG(FWSRAM_BASE), reg.reg);
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break;
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case 5:
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reg_write(FWSRAM_TOP_SDA_CFG(FWSRAM_BASE), reg.reg);
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break;
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case 7:
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reg_write(FWSRAM_TOP_TDO_CFG(FWSRAM_BASE), reg.reg);
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break;
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case 8:
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reg_write(FWSRAM_TOP_GPIO2_0_CFG(FWSRAM_BASE), reg.reg);
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break;
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case 10:
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case 11:
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case 12:
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case 13:
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case 14:
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case 15:
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case 16:
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reg_write(FWSRAM_BASE + FWSRAM_TOP_GPIO2_1_CFG_OFFS +
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((pin - 10) * 4), reg.reg);
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break;
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default:
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reg_write(TOP_BASE + (pin * 4), reg.reg);
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break;
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}
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}
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int top_set_pin(int pin, int func)
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{
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TOP_PINMUX_t reg;
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/* check global range */
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if ((pin < 0) || (pin > 170) || (func < 0) || (func > 3))
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return -1; /* pin number or function out of valid range */
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/* check undefined values; */
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if ((pin == 2) || (pin == 3) || (pin == 6) || (pin == 9))
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return -1; /* pin number out of valid range */
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reg = top_read_pin(pin);
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reg.Bits.funsel = func;
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top_write_pin(pin, reg);
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return 0;
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}
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#endif
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#if defined(CONFIG_VCT_PLATINUMAVC)
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int top_set_pin(int pin, int func)
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{
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TOP_PINMUX_t reg;
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/* check global range */
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if ((pin < 0) || (pin > 158))
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return -1; /* pin number or function out of valid range */
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reg.reg = reg_read(TOP_BASE + (pin * 4));
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reg.Bits.funsel = func;
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reg_write(TOP_BASE + (pin * 4), reg.reg);
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return 0;
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}
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#endif
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void vct_pin_mux_initialize(void)
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{
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#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
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top_set_pin(34, 01); /* EBI_CS0 */
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top_set_pin(33, 01); /* EBI_CS1 */
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top_set_pin(32, 01); /* EBI_CS2 */
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top_set_pin(100, 02); /* EBI_CS3 */
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top_set_pin(101, 02); /* EBI_CS4 */
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top_set_pin(102, 02); /* EBI_CS5 */
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top_set_pin(103, 02); /* EBI_CS6 */
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top_set_pin(104, 02); /* EBI_CS7 top_set_pin(104,03); EBI_GENIO3 */
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top_set_pin(35, 01); /* EBI_ALE */
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top_set_pin(36, 01); /* EBI_ADDR15 */
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top_set_pin(37, 01); /* EBI_ADDR14 top_set_pin(78,03); EBI_ADDR14 */
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top_set_pin(38, 01); /* EBI_ADDR13 */
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top_set_pin(39, 01); /* EBI_ADDR12 */
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top_set_pin(40, 01); /* EBI_ADDR11 */
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top_set_pin(41, 01); /* EBI_ADDR10 */
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top_set_pin(42, 01); /* EBI_ADDR9 */
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top_set_pin(43, 01); /* EBI_ADDR8 */
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top_set_pin(44, 01); /* EBI_ADDR7 */
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top_set_pin(45, 01); /* EBI_ADDR6 */
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top_set_pin(46, 01); /* EBI_ADDR5 */
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top_set_pin(47, 01); /* EBI_ADDR4 */
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top_set_pin(48, 01); /* EBI_ADDR3 */
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top_set_pin(49, 01); /* EBI_ADDR2 */
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top_set_pin(50, 01); /* EBI_ADDR1 */
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top_set_pin(51, 01); /* EBI_ADDR0 */
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top_set_pin(52, 01); /* EBI_DIR */
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top_set_pin(53, 01); /* EBI_DAT15 top_set_pin(81,01); EBI_DAT15 */
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top_set_pin(54, 01); /* EBI_DAT14 top_set_pin(82,01); EBI_DAT14 */
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top_set_pin(55, 01); /* EBI_DAT13 top_set_pin(83,01); EBI_DAT13 */
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top_set_pin(56, 01); /* EBI_DAT12 top_set_pin(84,01); EBI_DAT12 */
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top_set_pin(57, 01); /* EBI_DAT11 top_set_pin(85,01); EBI_DAT11 */
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top_set_pin(58, 01); /* EBI_DAT10 top_set_pin(86,01); EBI_DAT10 */
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top_set_pin(59, 01); /* EBI_DAT9 top_set_pin(87,01); EBI_DAT9 */
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top_set_pin(60, 01); /* EBI_DAT8 top_set_pin(88,01); EBI_DAT8 */
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top_set_pin(61, 01); /* EBI_DAT7 */
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top_set_pin(62, 01); /* EBI_DAT6 */
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top_set_pin(63, 01); /* EBI_DAT5 */
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top_set_pin(64, 01); /* EBI_DAT4 */
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top_set_pin(65, 01); /* EBI_DAT3 */
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top_set_pin(66, 01); /* EBI_DAT2 */
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top_set_pin(67, 01); /* EBI_DAT1 */
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top_set_pin(68, 01); /* EBI_DAT0 */
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top_set_pin(69, 01); /* EBI_IORD */
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top_set_pin(70, 01); /* EBI_IOWR */
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top_set_pin(71, 01); /* EBI_WE */
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top_set_pin(72, 01); /* EBI_OE */
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top_set_pin(73, 01); /* EBI_IORDY */
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top_set_pin(95, 02); /* EBI_EBI_DMACK*/
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top_set_pin(112, 02); /* EBI_IRQ0 */
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top_set_pin(111, 02); /* EBI_IRQ1 top_set_pin(111,03); EBI_DMARQ */
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top_set_pin(107, 02); /* EBI_IRQ2 */
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top_set_pin(108, 02); /* EBI_IRQ3 */
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top_set_pin(30, 01); /* EBI_GENIO1 top_set_pin(99,03); EBI_GENIO1 */
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top_set_pin(31, 01); /* EBI_GENIO2 top_set_pin(98,03); EBI_GENIO2 */
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top_set_pin(105, 02); /* EBI_GENIO3 top_set_pin(104,03); EBI_GENIO3 */
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top_set_pin(106, 02); /* EBI_GENIO4 top_set_pin(144,02); EBI_GENIO4 */
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top_set_pin(109, 02); /* EBI_GENIO5 top_set_pin(142,02); EBI_GENIO5 */
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top_set_pin(110, 02); /* EBI_BURST_CLK */
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#endif
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#if defined(CONFIG_VCT_PLATINUMAVC)
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top_set_pin(19, 01); /* EBI_CS0 */
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top_set_pin(18, 01); /* EBI_CS1 */
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top_set_pin(17, 01); /* EBI_CS2 */
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top_set_pin(92, 02); /* EBI_CS3 */
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top_set_pin(93, 02); /* EBI_CS4 */
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top_set_pin(95, 02); /* EBI_CS6 */
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top_set_pin(96, 02); /* EBI_CS7 top_set_pin(104,03); EBI_GENIO3 */
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top_set_pin(20, 01); /* EBI_ALE */
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top_set_pin(21, 01); /* EBI_ADDR15 */
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top_set_pin(22, 01); /* EBI_ADDR14 top_set_pin(78,03); EBI_ADDR14 */
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top_set_pin(23, 01); /* EBI_ADDR13 */
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top_set_pin(24, 01); /* EBI_ADDR12 */
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top_set_pin(25, 01); /* EBI_ADDR11 */
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top_set_pin(26, 01); /* EBI_ADDR10 */
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top_set_pin(27, 01); /* EBI_ADDR9 */
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top_set_pin(28, 01); /* EBI_ADDR8 */
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top_set_pin(29, 01); /* EBI_ADDR7 */
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top_set_pin(30, 01); /* EBI_ADDR6 */
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top_set_pin(31, 01); /* EBI_ADDR5 */
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top_set_pin(32, 01); /* EBI_ADDR4 */
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top_set_pin(33, 01); /* EBI_ADDR3 */
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top_set_pin(34, 01); /* EBI_ADDR2 */
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top_set_pin(35, 01); /* EBI_ADDR1 */
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top_set_pin(36, 01); /* EBI_ADDR0 */
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top_set_pin(37, 01); /* EBI_DIR */
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top_set_pin(38, 01); /* EBI_DAT15 top_set_pin(81,01); EBI_DAT15 */
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top_set_pin(39, 01); /* EBI_DAT14 top_set_pin(82,01); EBI_DAT14 */
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top_set_pin(40, 01); /* EBI_DAT13 top_set_pin(83,01); EBI_DAT13 */
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top_set_pin(41, 01); /* EBI_DAT12 top_set_pin(84,01); EBI_DAT12 */
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top_set_pin(42, 01); /* EBI_DAT11 top_set_pin(85,01); EBI_DAT11 */
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top_set_pin(43, 01); /* EBI_DAT10 top_set_pin(86,01); EBI_DAT10 */
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top_set_pin(44, 01); /* EBI_DAT9 top_set_pin(87,01); EBI_DAT9 */
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top_set_pin(45, 01); /* EBI_DAT8 top_set_pin(88,01); EBI_DAT8 */
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top_set_pin(46, 01); /* EBI_DAT7 */
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top_set_pin(47, 01); /* EBI_DAT6 */
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top_set_pin(48, 01); /* EBI_DAT5 */
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top_set_pin(49, 01); /* EBI_DAT4 */
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top_set_pin(50, 01); /* EBI_DAT3 */
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top_set_pin(51, 01); /* EBI_DAT2 */
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top_set_pin(52, 01); /* EBI_DAT1 */
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top_set_pin(53, 01); /* EBI_DAT0 */
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top_set_pin(54, 01); /* EBI_IORD */
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top_set_pin(55, 01); /* EBI_IOWR */
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top_set_pin(56, 01); /* EBI_WE */
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top_set_pin(57, 01); /* EBI_OE */
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top_set_pin(58, 01); /* EBI_IORDY */
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top_set_pin(87, 02); /* EBI_EBI_DMACK*/
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top_set_pin(106, 02); /* EBI_IRQ0 */
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top_set_pin(105, 02); /* EBI_IRQ1 top_set_pin(111,03); EBI_DMARQ */
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top_set_pin(101, 02); /* EBI_IRQ2 */
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top_set_pin(102, 02); /* EBI_IRQ3 */
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top_set_pin(15, 01); /* EBI_GENIO1 top_set_pin(99,03); EBI_GENIO1 */
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top_set_pin(16, 01); /* EBI_GENIO2 top_set_pin(98,03); EBI_GENIO2 */
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top_set_pin(99, 02); /* EBI_GENIO3 top_set_pin(104,03); EBI_GENIO3 */
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top_set_pin(100, 02); /* EBI_GENIO4 top_set_pin(144,02); EBI_GENIO4 */
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top_set_pin(103, 02); /* EBI_GENIO5 top_set_pin(142,02); EBI_GENIO5 */
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top_set_pin(104, 02); /* EBI_BURST_CLK */
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#endif
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/* I2C: Configure I2C-2 as GPIO to enable soft-i2c */
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top_set_pin(0, 2); /* SCL2 on GPIO 11 */
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top_set_pin(1, 2); /* SDA2 on GPIO 10 */
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/* UART pins */
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#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
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top_set_pin(141, 1);
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top_set_pin(143, 1);
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#endif
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#if defined(CONFIG_VCT_PLATINUMAVC)
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top_set_pin(107, 1);
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top_set_pin(109, 1);
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#endif
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}
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