mirror of
https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
199 lines
4 KiB
C
199 lines
4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2013 - 2017 Xilinx Inc.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <malloc.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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#define SLCR_LOCK_MAGIC 0x767B
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#define SLCR_UNLOCK_MAGIC 0xDF0D
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#define SLCR_NAND_L2_SEL 0x10
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#define SLCR_NAND_L2_SEL_MASK 0x1F
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#define SLCR_USB_L1_SEL 0x04
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#define SLCR_IDCODE_MASK 0x1F000
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#define SLCR_IDCODE_SHIFT 12
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/*
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* zynq_slcr_mio_get_status - Get the status of MIO peripheral.
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*
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* @peri_name: Name of the peripheral for checking MIO status
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* @get_pins: Pointer to array of get pin for this peripheral
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* @num_pins: Number of pins for this peripheral
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* @mask: Mask value
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* @check_val: Required check value to get the status of periph
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*/
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struct zynq_slcr_mio_get_status {
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const char *peri_name;
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const int *get_pins;
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int num_pins;
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u32 mask;
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u32 check_val;
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};
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static const int nand8_pins[] = {
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0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
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};
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static const int nand16_pins[] = {
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16, 17, 18, 19, 20, 21, 22, 23
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};
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static const int usb0_pins[] = {
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28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
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};
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static const int usb1_pins[] = {
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40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51
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};
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static const struct zynq_slcr_mio_get_status mio_periphs[] = {
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{
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"nand8",
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nand8_pins,
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ARRAY_SIZE(nand8_pins),
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SLCR_NAND_L2_SEL_MASK,
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SLCR_NAND_L2_SEL,
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},
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{
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"nand16",
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nand16_pins,
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ARRAY_SIZE(nand16_pins),
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SLCR_NAND_L2_SEL_MASK,
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SLCR_NAND_L2_SEL,
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},
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{
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"usb0",
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usb0_pins,
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ARRAY_SIZE(usb0_pins),
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SLCR_USB_L1_SEL,
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SLCR_USB_L1_SEL,
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},
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{
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"usb1",
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usb1_pins,
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ARRAY_SIZE(usb1_pins),
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SLCR_USB_L1_SEL,
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SLCR_USB_L1_SEL,
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},
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};
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static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
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void zynq_slcr_lock(void)
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{
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if (!slcr_lock) {
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writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
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slcr_lock = 1;
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}
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}
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void zynq_slcr_unlock(void)
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{
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if (slcr_lock) {
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writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
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slcr_lock = 0;
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}
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}
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/* Reset the entire system */
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void zynq_slcr_cpu_reset(void)
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{
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/*
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* Unlock the SLCR then reset the system.
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* Note that this seems to require raw i/o
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* functions or there's a lockup?
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*/
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zynq_slcr_unlock();
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/*
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* Clear 0x0F000000 bits of reboot status register to workaround
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* the FSBL not loading the bitstream after soft-reboot
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* This is a temporary solution until we know more.
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*/
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clrbits_le32(&slcr_base->reboot_status, 0xF000000);
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writel(1, &slcr_base->pss_rst_ctrl);
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}
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void zynq_slcr_devcfg_disable(void)
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{
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u32 reg_val;
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zynq_slcr_unlock();
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/* Disable AXI interface by asserting FPGA resets */
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writel(0xF, &slcr_base->fpga_rst_ctrl);
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/* Disable Level shifters before setting PS-PL */
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reg_val = readl(&slcr_base->lvl_shftr_en);
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reg_val &= ~0xF;
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writel(reg_val, &slcr_base->lvl_shftr_en);
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/* Set Level Shifters DT618760 */
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writel(0xA, &slcr_base->lvl_shftr_en);
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zynq_slcr_lock();
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}
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void zynq_slcr_devcfg_enable(void)
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{
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zynq_slcr_unlock();
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/* Set Level Shifters DT618760 */
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writel(0xF, &slcr_base->lvl_shftr_en);
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/* Enable AXI interface by de-asserting FPGA resets */
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writel(0x0, &slcr_base->fpga_rst_ctrl);
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zynq_slcr_lock();
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}
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u32 zynq_slcr_get_boot_mode(void)
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{
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/* Get the bootmode register value */
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return readl(&slcr_base->boot_mode);
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}
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u32 zynq_slcr_get_idcode(void)
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{
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return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
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SLCR_IDCODE_SHIFT;
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}
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/*
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* zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral.
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*
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* @periph: Name of the peripheral
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*
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* Returns count to indicate the number of pins configured for the
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* given @periph.
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*/
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int zynq_slcr_get_mio_pin_status(const char *periph)
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{
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const struct zynq_slcr_mio_get_status *mio_ptr;
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int val, j;
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int mio = 0;
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u32 i;
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for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) {
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if (strcmp(periph, mio_periphs[i].peri_name) == 0) {
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mio_ptr = &mio_periphs[i];
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for (j = 0; j < mio_ptr->num_pins; j++) {
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val = readl(&slcr_base->mio_pin
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[mio_ptr->get_pins[j]]);
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if ((val & mio_ptr->mask) == mio_ptr->check_val)
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mio++;
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}
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break;
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}
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}
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return mio;
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}
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