mirror of
https://github.com/AsahiLinux/u-boot
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14f643d1a2
Add Apollo Lake ASL files, taken from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
173 lines
4 KiB
Text
173 lines
4 KiB
Text
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016 Intel Corporation.
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*/
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Scope (\_SB.PCI0) {
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/* 0xD6- is the port address */
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/* 0x600- is the dynamic clock gating control register offset (GENR) */
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OperationRegion (SBMM, SystemMemory,
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Or ( Or (IOMAP_P2SB_BAR,
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ShiftLeft(0xD6, PCR_PORTID_SHIFT)), 0x0600), 0x18)
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Field (SBMM, DWordAcc, NoLock, Preserve)
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{
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GENR, 32,
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Offset (0x08),
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, 5, /* bit[5] represents Force Card Detect SD Card */
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GRR3, 1, /* GPPRVRW3 for SD Card detect Bypass. It's active high */
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}
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/* SCC power gate control method, this method must be serialized as
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* multiple device will control the GENR register
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*
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* Arguments: (2)
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* Arg0: 0-AND 1-OR
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* Arg1: Value
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*/
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Method (SCPG, 2, Serialized)
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{
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if (LEqual(Arg0, 0x1)) {
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Or (^GENR, Arg1, ^GENR)
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} ElseIf (LEqual(Arg0, 0x0)){
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And (^GENR, Arg1, ^GENR)
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}
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}
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/* eMMC */
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Device (SDHA) {
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Name (_ADR, 0x001C0000)
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Name (_DDN, "Intel(R) eMMC Controller - 80865ACC")
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Name (UUID, ToUUID ("E5C937D0-3553-4D7A-9117-EA4D19C3434D"))
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/*
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* Device Specific Method
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* Arg0 - UUID
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* Arg1 - Revision
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* Arg2 - Function Index
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*/
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Method (_DSM, 4)
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{
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If (LEqual (Arg0, ^UUID)) {
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/*
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* Function 9: Device Readiness Durations
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* Returns a package of five integers covering
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* various device related delays in PCIe Base Spec.
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*/
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If (LEqual (Arg2, 9)) {
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/*
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* Function 9 support for revision 3.
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* ECN link for function definitions
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* [https://pcisig.com/sites/default/files/
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* specification_documents/
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* ECN_fw_latency_optimization_final.pdf]
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*/
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If (LEqual (Arg1, 3)) {
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/*
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* Integer 0: FW reset time.
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* Integer 1: FW data link up time.
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* Integer 2: FW functional level reset
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* time.
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* Integer 3: FW D3 hot to D0 time.
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* Integer 4: FW VF enable time.
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* set ACPI constant Ones for elements
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* where overriding the default value
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* is not desired.
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*/
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Return (Package (5) {0, Ones, Ones,
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Ones, Ones})
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}
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}
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}
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Return (Buffer() { 0x00 })
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}
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Method (_PS0, 0, NotSerialized)
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{
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/* Clear clock gate
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* Clear bit 6 and 0
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*/
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^^SCPG(0,0xFFFFFFBE)
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/* Sleep 2 ms */
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Sleep (2)
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}
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Method (_PS3, 0, NotSerialized)
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{
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/* Enable power gate
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* Restore clock gate
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* Restore bit 6 and 0
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*/
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^^SCPG(1,0x00000041)
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}
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Device (CARD)
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{
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Name (_ADR, 0x00000008)
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Method (_RMV, 0, NotSerialized)
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{
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Return (0)
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}
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}
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} /* Device (SDHA) */
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/* SD CARD */
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Device (SDCD)
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{
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Name (_ADR, 0x001B0000)
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Name (_S0W, 4) /* _S0W: S0 Device Wake State */
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Name (SCD0, 0) /* Store SD_CD DW0 address */
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/* Set the host ownership of sdcard cd during kernel boot */
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Method (_INI, 0)
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{
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/* Check SDCard CD port is valid */
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If (LAnd (LNotEqual (\SCDP, 0), LNotEqual (\SCDO, 0) ))
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{
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/* Store DW0 address of SD_CD */
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Store (GDW0 (\SCDP, \SCDO), SCD0)
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/* Get the current SD_CD ownership */
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Store (\_SB.GHO (\SCDP, \SCDO), Local0)
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/* Set host ownership as GPIO in HOSTSW_OWN reg */
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Or (Local0, ShiftLeft (1, Mod (\SCDO, 32)), Local0)
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\_SB.SHO (\SCDP, \SCDO, Local0)
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}
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}
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Method (_PS0, 0, NotSerialized)
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{
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/* Check SDCard CD port is valid */
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If (LAnd (LNotEqual (\SCDP, 0), LNotEqual (\SCDO, 0) ))
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{
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/* Store DW0 into local0 to get rxstate of GPIO */
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Store (\_SB.GPC0 (SCD0), Local0)
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/* Extract rxstate [bit 1] of sdcard card detect pin */
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And (Local0, PAD_CFG0_RX_STATE, Local0)
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/* If the sdcard is present, rxstate is low.
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* If sdcard is not present, rxstate is High.
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* Write the inverted value of rxstate to GRR3.
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*/
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If (LEqual (Local0, 0)) {
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Store (1, ^^GRR3)
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} Else {
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Store (0, ^^GRR3)
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}
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Sleep (2)
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}
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}
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Method (_PS3, 0, NotSerialized)
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{
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/* Clear GRR3 to Power Gate SD Controller */
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Store (0, ^^GRR3)
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}
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Device (CARD)
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{
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Name (_ADR, 0x00000008)
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Method (_RMV, 0, NotSerialized)
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{
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Return (1)
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}
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}
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} /* Device (SDCD) */
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}
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