mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 10:18:38 +00:00
48b42616e9
- rewrite of the S3C24X0 register definitions stuff
- "driver" for the built-in S3C24X0 RTC
* Patches by Yuli Barcohen, 12 Jun 2003:
- Add MII support and Ethernet PHY initialization for MPC8260ADS board
- Fix incorrect SIUMCR initialisation caused by wrong Hard Reset
configuration word supplied by FPGA on some MPC8260ADS boards
* Patch by Pantelis Antoniou, 10 Jun 2003:
Unify status LED interface
126 lines
3 KiB
C
126 lines
3 KiB
C
/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <s3c2410.h>
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/* ------------------------------------------------------------------------- */
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#define FCLK_SPEED 1
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#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
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#define M_MDIV 0xC3
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#define M_PDIV 0x4
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#define M_SDIV 0x1
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#elif FCLK_SPEED==1 /* Fout = 202.8MHz */
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#define M_MDIV 0xA1
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#define M_PDIV 0x3
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#define M_SDIV 0x1
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#endif
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#define USB_CLOCK 1
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#if USB_CLOCK==0
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#define U_M_MDIV 0xA1
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#define U_M_PDIV 0x3
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#define U_M_SDIV 0x1
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#elif USB_CLOCK==1
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#define U_M_MDIV 0x48
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#define U_M_PDIV 0x3
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#define U_M_SDIV 0x2
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#endif
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static inline void delay (unsigned long loops)
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{
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__asm__ volatile ("1:\n"
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"subs %0, %1, #1\n"
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"bne 1b":"=r" (loops):"0" (loops));
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}
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/*
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* Miscellaneous platform dependent initialisations
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*/
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int board_init (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
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S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
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/* to reduce PLL lock time, adjust the LOCKTIME register */
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clk_power->LOCKTIME = 0xFFFFFF;
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/* configure MPLL */
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clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
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/* some delay between MPLL and UPLL */
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delay (4000);
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/* configure UPLL */
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clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
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/* some delay between MPLL and UPLL */
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delay (8000);
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/* set up the I/O ports */
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gpio->GPACON = 0x007FFFFF;
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gpio->GPBCON = 0x00044555;
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gpio->GPBUP = 0x000007FF;
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gpio->GPCCON = 0xAAAAAAAA;
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gpio->GPCUP = 0x0000FFFF;
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gpio->GPDCON = 0xAAAAAAAA;
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gpio->GPDUP = 0x0000FFFF;
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gpio->GPECON = 0xAAAAAAAA;
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gpio->GPEUP = 0x0000FFFF;
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gpio->GPFCON = 0x000055AA;
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gpio->GPFUP = 0x000000FF;
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gpio->GPGCON = 0xFF95FFBA;
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gpio->GPGUP = 0x0000FFFF;
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gpio->GPHCON = 0x002AFAAA;
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gpio->GPHUP = 0x000007FF;
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/* arch number of SMDK2410-Board */
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gd->bd->bi_arch_number = 193;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = 0x30000100;
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icache_enable();
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dcache_enable();
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return 0;
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}
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int dram_init (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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