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https://github.com/AsahiLinux/u-boot
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ecc8d425fd
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
341 lines
9 KiB
C
341 lines
9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2020 NXP
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* Layerscape PCIe EP driver
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*/
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#include <common.h>
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#include <asm/arch/fsl_serdes.h>
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#include <dm.h>
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#include <asm/global_data.h>
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#include <dm/devres.h>
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#include <errno.h>
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#include <pci_ep.h>
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#include <asm/io.h>
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#include <linux/sizes.h>
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#include <linux/log2.h>
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#include "pcie_layerscape.h"
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DECLARE_GLOBAL_DATA_PTR;
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static void ls_pcie_ep_enable_cfg(struct ls_pcie_ep *pcie_ep)
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{
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struct ls_pcie *pcie = pcie_ep->pcie;
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u32 config;
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config = ctrl_readl(pcie, PCIE_PF_CONFIG);
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config |= PCIE_CONFIG_READY;
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ctrl_writel(pcie, config, PCIE_PF_CONFIG);
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}
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static int ls_ep_set_bar(struct udevice *dev, uint fn, struct pci_bar *ep_bar)
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{
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struct ls_pcie_ep *pcie_ep = dev_get_priv(dev);
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struct ls_pcie *pcie = pcie_ep->pcie;
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dma_addr_t bar_phys = ep_bar->phys_addr;
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enum pci_barno bar = ep_bar->barno;
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u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
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int flags = ep_bar->flags;
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int type, idx;
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u64 size;
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idx = bar;
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/* BAR size is 2^(aperture + 11) */
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size = max_t(size_t, ep_bar->size, FSL_PCIE_EP_MIN_APERTURE);
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if (!(flags & PCI_BASE_ADDRESS_SPACE))
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type = PCIE_ATU_TYPE_MEM;
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else
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type = PCIE_ATU_TYPE_IO;
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ls_pcie_atu_inbound_set(pcie, fn, 0, type, idx, bar, bar_phys);
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dbi_writel(pcie, lower_32_bits(size - 1), reg + PCIE_NO_SRIOV_BAR_BASE);
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dbi_writel(pcie, flags, reg);
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if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
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dbi_writel(pcie, upper_32_bits(size - 1),
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reg + 4 + PCIE_NO_SRIOV_BAR_BASE);
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dbi_writel(pcie, 0, reg + 4);
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}
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return 0;
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}
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static struct pci_ep_ops ls_pcie_ep_ops = {
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.set_bar = ls_ep_set_bar,
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};
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static void ls_pcie_ep_setup_atu(struct ls_pcie_ep *pcie_ep, u32 pf)
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{
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struct ls_pcie *pcie = pcie_ep->pcie;
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u32 vf_flag = 0;
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u64 phys = 0;
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phys = CFG_SYS_PCI_EP_MEMORY_BASE + pf * SZ_64M;
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phys = ALIGN(phys, PCIE_BAR0_SIZE);
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/* ATU 0 : INBOUND : map BAR0 */
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ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
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0 + pf * BAR_NUM, 0, phys);
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/* ATU 1 : INBOUND : map BAR1 */
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phys = ALIGN(phys + PCIE_BAR0_SIZE, PCIE_BAR1_SIZE);
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ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
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1 + pf * BAR_NUM, 1, phys);
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/* ATU 2 : INBOUND : map BAR2 */
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phys = ALIGN(phys + PCIE_BAR1_SIZE, PCIE_BAR2_SIZE);
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ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
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2 + pf * BAR_NUM, 2, phys);
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/* ATU 3 : INBOUND : map BAR2 */
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phys = ALIGN(phys + PCIE_BAR2_SIZE, PCIE_BAR4_SIZE);
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ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
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3 + pf * BAR_NUM, 4, phys);
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if (pcie_ep->sriov_flag) {
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vf_flag = 1;
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/* ATU 4 : INBOUND : map BAR0 */
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phys = ALIGN(phys + PCIE_BAR4_SIZE, PCIE_BAR0_SIZE);
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ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
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4 + pf * BAR_NUM, 0, phys);
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/* ATU 5 : INBOUND : map BAR1 */
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phys = ALIGN(phys + PCIE_BAR0_SIZE * PCIE_VF_NUM,
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PCIE_BAR1_SIZE);
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ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
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5 + pf * BAR_NUM, 1, phys);
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/* ATU 6 : INBOUND : map BAR2 */
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phys = ALIGN(phys + PCIE_BAR1_SIZE * PCIE_VF_NUM,
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PCIE_BAR2_SIZE);
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ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
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6 + pf * BAR_NUM, 2, phys);
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/* ATU 7 : INBOUND : map BAR4 */
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phys = ALIGN(phys + PCIE_BAR2_SIZE * PCIE_VF_NUM,
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PCIE_BAR4_SIZE);
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ls_pcie_atu_inbound_set(pcie, pf, vf_flag, PCIE_ATU_TYPE_MEM,
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7 + pf * BAR_NUM, 4, phys);
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}
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/* ATU: OUTBOUND : map MEM */
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ls_pcie_atu_outbound_set(pcie, pf, PCIE_ATU_TYPE_MEM,
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(u64)pcie_ep->addr_res.start +
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pf * CFG_SYS_PCI_MEMORY_SIZE,
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0, CFG_SYS_PCI_MEMORY_SIZE);
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}
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/* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */
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static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
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{
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u32 mask;
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/* The least inbound window is 4KiB */
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if (size < SZ_4K)
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mask = 0;
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else
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mask = size - 1;
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switch (bar) {
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case 0:
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writel(mask, bar_base + PCI_BASE_ADDRESS_0);
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break;
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case 1:
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writel(mask, bar_base + PCI_BASE_ADDRESS_1);
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break;
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case 2:
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writel(mask, bar_base + PCI_BASE_ADDRESS_2);
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writel(0, bar_base + PCI_BASE_ADDRESS_3);
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break;
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case 4:
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writel(mask, bar_base + PCI_BASE_ADDRESS_4);
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writel(0, bar_base + PCI_BASE_ADDRESS_5);
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break;
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default:
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break;
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}
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}
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static void ls_pcie_ep_setup_bars(void *bar_base)
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{
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/* BAR0 - 32bit - MEM */
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ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
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/* BAR1 - 32bit - MEM*/
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ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
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/* BAR2 - 64bit - MEM */
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ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
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/* BAR4 - 64bit - MEM */
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ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
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}
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static void ls_pcie_ep_setup_vf_bars(void *bar_base)
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{
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/* VF BAR0 MASK register at offset 0x19c*/
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bar_base += PCIE_SRIOV_VFBAR0 - PCI_BASE_ADDRESS_0;
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/* VF-BAR0 - 32bit - MEM */
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ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
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/* VF-BAR1 - 32bit - MEM*/
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ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
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/* VF-BAR2 - 64bit - MEM */
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ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
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/* VF-BAR4 - 64bit - MEM */
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ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
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}
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static void ls_pcie_setup_ep(struct ls_pcie_ep *pcie_ep)
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{
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u32 sriov;
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u32 pf, vf;
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void *bar_base = NULL;
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struct ls_pcie *pcie = pcie_ep->pcie;
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sriov = readl(pcie->dbi + PCIE_SRIOV);
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if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) {
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pcie_ep->sriov_flag = 1;
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for (pf = 0; pf < PCIE_PF_NUM; pf++) {
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/*
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* The VF_BARn_REG register's Prefetchable and Type bit
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* fields are overwritten by a write to VF's BAR Mask
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* register. Before writing to the VF_BARn_MASK_REG
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* register, write 0b to the PCIE_MISC_CONTROL_1_OFF
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* register.
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*/
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writel(0, pcie->dbi + PCIE_MISC_CONTROL_1_OFF);
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bar_base = pcie->dbi +
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PCIE_MASK_OFFSET(pcie_ep->cfg2_flag, pf,
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pcie_ep->pf1_offset);
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if (pcie_ep->cfg2_flag) {
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ctrl_writel(pcie,
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PCIE_LCTRL0_VAL(pf, 0),
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PCIE_PF_VF_CTRL);
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ls_pcie_ep_setup_bars(bar_base);
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for (vf = 1; vf <= PCIE_VF_NUM; vf++) {
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ctrl_writel(pcie,
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PCIE_LCTRL0_VAL(pf, vf),
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PCIE_PF_VF_CTRL);
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ls_pcie_ep_setup_vf_bars(bar_base);
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}
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} else {
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ls_pcie_ep_setup_bars(bar_base);
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ls_pcie_ep_setup_vf_bars(bar_base);
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}
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ls_pcie_ep_setup_atu(pcie_ep, pf);
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}
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if (pcie_ep->cfg2_flag) /* Disable CFG2 */
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ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL);
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} else {
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ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
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ls_pcie_ep_setup_atu(pcie_ep, 0);
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}
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ls_pcie_dump_atu(pcie, PCIE_ATU_REGION_NUM_SRIOV,
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PCIE_ATU_REGION_INBOUND);
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ls_pcie_ep_enable_cfg(pcie_ep);
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}
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static int ls_pcie_ep_probe(struct udevice *dev)
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{
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struct ls_pcie_ep *pcie_ep = dev_get_priv(dev);
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struct ls_pcie *pcie;
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u16 link_sta;
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int ret;
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u32 svr;
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pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
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if (!pcie)
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return -ENOMEM;
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pcie_ep->pcie = pcie;
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pcie->dbi = (void __iomem *)devfdt_get_addr_index(dev, 0);
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if (!pcie->dbi)
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return -ENOMEM;
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pcie->ctrl = (void __iomem *)devfdt_get_addr_index(dev, 1);
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if (!pcie->ctrl)
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return -ENOMEM;
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ret = fdt_get_named_resource(gd->fdt_blob, dev_of_offset(dev),
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"reg", "reg-names",
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"addr_space", &pcie_ep->addr_res);
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if (ret) {
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printf("%s: resource \"addr_space\" not found\n", dev->name);
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return ret;
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}
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pcie->idx = ((unsigned long)pcie->dbi - PCIE_SYS_BASE_ADDR) /
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PCIE_CCSR_SIZE;
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/* This controller is disabled by RCW */
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if (!is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx)))
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return 0;
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pcie->big_endian = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
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"big-endian");
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svr = SVR_SOC_VER(get_svr());
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if (svr == SVR_LX2160A || svr == SVR_LX2162A ||
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svr == SVR_LX2120A || svr == SVR_LX2080A ||
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svr == SVR_LX2122A || svr == SVR_LX2082A)
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pcie_ep->pf1_offset = LX2160_PCIE_PF1_OFFSET;
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else
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pcie_ep->pf1_offset = LS_PCIE_PF1_OFFSET;
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if (svr == SVR_LS2080A || svr == SVR_LS2085A)
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pcie_ep->cfg2_flag = 1;
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else
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pcie_ep->cfg2_flag = 0;
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pcie->mode = readb(pcie->dbi + PCI_HEADER_TYPE) & 0x7f;
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if (pcie->mode != PCI_HEADER_TYPE_NORMAL)
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return 0;
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pcie_ep->max_functions = fdtdec_get_int(gd->fdt_blob,
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dev_of_offset(dev),
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"max-functions", 1);
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pcie_ep->num_ib_wins = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"num-ib-windows", 8);
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pcie_ep->num_ob_wins = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"num-ob-windows", 8);
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printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
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"Endpoint");
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ls_pcie_setup_ep(pcie_ep);
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if (!ls_pcie_link_up(pcie)) {
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/* Let the user know there's no PCIe link */
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printf(": no link\n");
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return 0;
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}
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/* Print the negotiated PCIe link width */
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link_sta = readw(pcie->dbi + PCIE_LINK_STA);
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printf(": x%d gen%d\n", (link_sta & PCIE_LINK_WIDTH_MASK) >> 4,
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link_sta & PCIE_LINK_SPEED_MASK);
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return 0;
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}
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static int ls_pcie_ep_remove(struct udevice *dev)
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{
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return 0;
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}
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const struct udevice_id ls_pcie_ep_ids[] = {
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{ .compatible = "fsl,ls-pcie-ep" },
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{ }
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};
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U_BOOT_DRIVER(pci_layerscape_ep) = {
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.name = "pci_layerscape_ep",
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.id = UCLASS_PCI_EP,
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.of_match = ls_pcie_ep_ids,
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.ops = &ls_pcie_ep_ops,
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.probe = ls_pcie_ep_probe,
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.remove = ls_pcie_ep_remove,
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.priv_auto = sizeof(struct ls_pcie_ep),
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};
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