mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-21 02:33:07 +00:00
7c2d5d1642
After the discussion here: https://lore.kernel.org/netdev/20210603143453.if7hgifupx5k433b@pali/ which resulted in this patch: https://patchwork.kernel.org/project/netdevbpf/patch/20210704134325.24842-1-pali@kernel.org/ and many other discussions before it, notably: https://patchwork.kernel.org/project/linux-arm-kernel/patch/1512016235-15909-1-git-send-email-Bhaskar.Upadhaya@nxp.com/ it became apparent that nobody really knows what "SGMII 2500" is. Certainly, Freescale/NXP hardware engineers name this protocol "SGMII 2500" in the reference manuals, but the PCS devices do not support any "SGMII" specific features when operating at the speed of 2500 Mbps, no in-band autoneg and no speed change via symbol replication . So that leaves a fixed speed of 2500 Mbps using a coding of 8b/10b with a SERDES lane frequency of 3.125 GHz. In fact, "SGMII 2500 without in-band autoneg and at a fixed speed" is indistinguishable from "2500base-x without in-band autoneg", which is precisely what these NXP devices support. So it just appears that "SGMII 2500" is an unclear name with no clear definition that stuck. As such, in the Linux kernel, the drivers which use this SERDES protocol use the 2500base-x phy-mode. This patch converts U-Boot to use 2500base-x too, or at least, as much as it can. Note that I would have really liked to delete PHY_INTERFACE_MODE_SGMII_2500 completely, but the mvpp2 driver seems to even distinguish between SGMII 2500 and 2500base-X. Namely, it enables in-band autoneg for one but not the other, and forces flow control for one but not the other. This goes back to the idea that maybe 2500base-X is a fiber protocol and SGMII-2500 is an MII protocol (connects a MAC to a PHY such as Aquantia), but the two are practically indistinguishable through everything except use case. NXP devices can support both use cases through an identical configuration, for example RX flow control can be unconditionally enabled in order to support rate adaptation performed by an Aquantia PHY. At least I can find no indication in online documents published by Cisco which would point towards "SGMII-2500" being an actual standard with an actual definition, so I cannot say "yes, NXP devices support it". Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
44 lines
1,018 B
C
44 lines
1,018 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
/*
|
|
* Copyright 2017 NXP
|
|
*/
|
|
|
|
#define ETH_1_1G_BUS_ID 0x1
|
|
#define ETH_1_1G_PHY_ID 0x1e
|
|
#define ETH_1_1G_MDIO_MUX 0x2
|
|
#define ETH_1G_MDIO_PHY_MASK 0xBFFFFFFD
|
|
#define ETH_1_1G_PHY_MODE "sgmii"
|
|
#define ETH_2_1G_BUS_ID 0x1
|
|
#define ETH_2_1G_PHY_ID 0x1
|
|
#define ETH_2_1G_MDIO_MUX 0x1
|
|
#define ETH_2_1G_PHY_MODE "rgmii"
|
|
|
|
#define ETH_1_2_5G_BUS_ID 0x0
|
|
#define ETH_1_2_5G_PHY_ID 0x1
|
|
#define ETH_1_2_5G_MDIO_MUX 0x2
|
|
#define ETH_2_5G_MDIO_PHY_MASK 0xFFFFFFF9
|
|
#define ETH_2_5G_PHY_MODE "2500base-x"
|
|
#define ETH_2_2_5G_BUS_ID 0x1
|
|
#define ETH_2_2_5G_PHY_ID 0x2
|
|
#define ETH_2_2_5G_MDIO_MUX 0x3
|
|
|
|
#define SERDES_1_G_PROTOCOL 0x3508
|
|
#define SERDES_2_5_G_PROTOCOL 0x2205
|
|
|
|
#define PFE_PROP_LEN 4
|
|
|
|
#define ETH_1_PATH "/pfe@04000000/ethernet@0"
|
|
#define ETH_1_MDIO ETH_1_PATH "/mdio@0"
|
|
|
|
#define ETH_2_PATH "/pfe@04000000/ethernet@1"
|
|
#define ETH_2_MDIO ETH_2_PATH "/mdio@0"
|
|
|
|
#define NUM_ETH_NODE 2
|
|
|
|
struct pfe_prop_val {
|
|
int busid;
|
|
int phyid;
|
|
int mux_val;
|
|
int phy_mask;
|
|
char *phy_mode;
|
|
};
|