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This is make naming consistent with the kernel and devicetree and in preparation of pulling out the common tegra20 code. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
354 lines
7.4 KiB
C
354 lines
7.4 KiB
C
/*
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* (C) Copyright 2010,2011
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* NVIDIA Corporation <www.nvidia.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _PINMUX_H_
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#define _PINMUX_H_
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/*
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* Pin groups which we adjust. There are three basic attributes of each pin
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* group which use this enum:
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*
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* - function
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* - pullup / pulldown
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* - tristate or normal
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*/
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enum pmux_pingrp {
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/* APB_MISC_PP_TRISTATE_REG_A_0 */
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PINGRP_ATA,
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PINGRP_ATB,
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PINGRP_ATC,
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PINGRP_ATD,
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PINGRP_CDEV1,
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PINGRP_CDEV2,
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PINGRP_CSUS,
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PINGRP_DAP1,
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PINGRP_DAP2,
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PINGRP_DAP3,
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PINGRP_DAP4,
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PINGRP_DTA,
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PINGRP_DTB,
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PINGRP_DTC,
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PINGRP_DTD,
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PINGRP_DTE,
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PINGRP_GPU,
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PINGRP_GPV,
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PINGRP_I2CP,
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PINGRP_IRTX,
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PINGRP_IRRX,
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PINGRP_KBCB,
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PINGRP_KBCA,
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PINGRP_PMC,
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PINGRP_PTA,
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PINGRP_RM,
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PINGRP_KBCE,
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PINGRP_KBCF,
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PINGRP_GMA,
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PINGRP_GMC,
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PINGRP_SDIO1,
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PINGRP_OWC,
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/* 32: APB_MISC_PP_TRISTATE_REG_B_0 */
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PINGRP_GME,
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PINGRP_SDC,
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PINGRP_SDD,
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PINGRP_RESERVED0,
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PINGRP_SLXA,
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PINGRP_SLXC,
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PINGRP_SLXD,
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PINGRP_SLXK,
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PINGRP_SPDI,
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PINGRP_SPDO,
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PINGRP_SPIA,
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PINGRP_SPIB,
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PINGRP_SPIC,
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PINGRP_SPID,
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PINGRP_SPIE,
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PINGRP_SPIF,
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PINGRP_SPIG,
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PINGRP_SPIH,
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PINGRP_UAA,
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PINGRP_UAB,
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PINGRP_UAC,
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PINGRP_UAD,
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PINGRP_UCA,
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PINGRP_UCB,
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PINGRP_RESERVED1,
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PINGRP_ATE,
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PINGRP_KBCC,
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PINGRP_RESERVED2,
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PINGRP_RESERVED3,
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PINGRP_GMB,
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PINGRP_GMD,
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PINGRP_DDC,
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/* 64: APB_MISC_PP_TRISTATE_REG_C_0 */
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PINGRP_LD0,
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PINGRP_LD1,
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PINGRP_LD2,
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PINGRP_LD3,
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PINGRP_LD4,
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PINGRP_LD5,
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PINGRP_LD6,
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PINGRP_LD7,
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PINGRP_LD8,
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PINGRP_LD9,
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PINGRP_LD10,
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PINGRP_LD11,
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PINGRP_LD12,
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PINGRP_LD13,
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PINGRP_LD14,
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PINGRP_LD15,
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PINGRP_LD16,
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PINGRP_LD17,
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PINGRP_LHP0,
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PINGRP_LHP1,
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PINGRP_LHP2,
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PINGRP_LVP0,
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PINGRP_LVP1,
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PINGRP_HDINT,
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PINGRP_LM0,
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PINGRP_LM1,
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PINGRP_LVS,
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PINGRP_LSC0,
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PINGRP_LSC1,
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PINGRP_LSCK,
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PINGRP_LDC,
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PINGRP_LCSN,
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/* 96: APB_MISC_PP_TRISTATE_REG_D_0 */
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PINGRP_LSPI,
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PINGRP_LSDA,
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PINGRP_LSDI,
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PINGRP_LPW0,
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PINGRP_LPW1,
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PINGRP_LPW2,
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PINGRP_LDI,
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PINGRP_LHS,
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PINGRP_LPP,
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PINGRP_RESERVED4,
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PINGRP_KBCD,
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PINGRP_GPU7,
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PINGRP_DTF,
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PINGRP_UDA,
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PINGRP_CRTP,
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PINGRP_SDB,
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/* these pin groups only have pullup and pull down control */
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PINGRP_FIRST_NO_MUX,
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PINGRP_CK32 = PINGRP_FIRST_NO_MUX,
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PINGRP_DDRC,
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PINGRP_PMCA,
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PINGRP_PMCB,
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PINGRP_PMCC,
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PINGRP_PMCD,
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PINGRP_PMCE,
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PINGRP_XM2C,
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PINGRP_XM2D,
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PINGRP_COUNT,
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};
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/*
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* Functions which can be assigned to each of the pin groups. The values here
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* bear no relation to the values programmed into pinmux registers and are
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* purely a convenience. The translation is done through a table search.
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*/
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enum pmux_func {
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PMUX_FUNC_AHB_CLK,
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PMUX_FUNC_APB_CLK,
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PMUX_FUNC_AUDIO_SYNC,
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PMUX_FUNC_CRT,
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PMUX_FUNC_DAP1,
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PMUX_FUNC_DAP2,
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PMUX_FUNC_DAP3,
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PMUX_FUNC_DAP4,
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PMUX_FUNC_DAP5,
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PMUX_FUNC_DISPA,
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PMUX_FUNC_DISPB,
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PMUX_FUNC_EMC_TEST0_DLL,
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PMUX_FUNC_EMC_TEST1_DLL,
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PMUX_FUNC_GMI,
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PMUX_FUNC_GMI_INT,
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PMUX_FUNC_HDMI,
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PMUX_FUNC_I2C,
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PMUX_FUNC_I2C2,
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PMUX_FUNC_I2C3,
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PMUX_FUNC_IDE,
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PMUX_FUNC_IRDA,
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PMUX_FUNC_KBC,
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PMUX_FUNC_MIO,
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PMUX_FUNC_MIPI_HS,
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PMUX_FUNC_NAND,
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PMUX_FUNC_OSC,
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PMUX_FUNC_OWR,
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PMUX_FUNC_PCIE,
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PMUX_FUNC_PLLA_OUT,
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PMUX_FUNC_PLLC_OUT1,
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PMUX_FUNC_PLLM_OUT1,
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PMUX_FUNC_PLLP_OUT2,
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PMUX_FUNC_PLLP_OUT3,
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PMUX_FUNC_PLLP_OUT4,
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PMUX_FUNC_PWM,
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PMUX_FUNC_PWR_INTR,
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PMUX_FUNC_PWR_ON,
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PMUX_FUNC_RTCK,
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PMUX_FUNC_SDIO1,
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PMUX_FUNC_SDIO2,
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PMUX_FUNC_SDIO3,
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PMUX_FUNC_SDIO4,
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PMUX_FUNC_SFLASH,
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PMUX_FUNC_SPDIF,
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PMUX_FUNC_SPI1,
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PMUX_FUNC_SPI2,
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PMUX_FUNC_SPI2_ALT,
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PMUX_FUNC_SPI3,
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PMUX_FUNC_SPI4,
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PMUX_FUNC_TRACE,
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PMUX_FUNC_TWC,
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PMUX_FUNC_UARTA,
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PMUX_FUNC_UARTB,
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PMUX_FUNC_UARTC,
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PMUX_FUNC_UARTD,
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PMUX_FUNC_UARTE,
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PMUX_FUNC_ULPI,
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PMUX_FUNC_VI,
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PMUX_FUNC_VI_SENSOR_CLK,
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PMUX_FUNC_XIO,
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PMUX_FUNC_SAFE,
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/* These don't have a name, but can be used in the table */
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PMUX_FUNC_RSVD1,
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PMUX_FUNC_RSVD2,
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PMUX_FUNC_RSVD3,
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PMUX_FUNC_RSVD4,
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PMUX_FUNC_RSVD, /* Not valid and should not be used */
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PMUX_FUNC_COUNT,
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PMUX_FUNC_NONE = -1,
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};
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/* return 1 if a pmux_func is in range */
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#define pmux_func_isvalid(func) ((func) >= 0 && (func) < PMUX_FUNC_COUNT && \
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(func) != PMUX_FUNC_RSVD)
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/* The pullup/pulldown state of a pin group */
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enum pmux_pull {
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PMUX_PULL_NORMAL = 0,
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PMUX_PULL_DOWN,
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PMUX_PULL_UP,
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};
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/* Defines whether a pin group is tristated or in normal operation */
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enum pmux_tristate {
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PMUX_TRI_NORMAL = 0,
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PMUX_TRI_TRISTATE = 1,
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};
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/* Available power domains used by pin groups */
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enum pmux_vddio {
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PMUX_VDDIO_BB = 0,
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PMUX_VDDIO_LCD,
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PMUX_VDDIO_VI,
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PMUX_VDDIO_UART,
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PMUX_VDDIO_DDR,
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PMUX_VDDIO_NAND,
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PMUX_VDDIO_SYS,
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PMUX_VDDIO_AUDIO,
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PMUX_VDDIO_SD,
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PMUX_VDDIO_NONE
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};
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enum {
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PMUX_TRISTATE_REGS = 4,
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PMUX_MUX_REGS = 7,
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PMUX_PULL_REGS = 5,
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};
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/* APB MISC Pin Mux and Tristate (APB_MISC_PP_) registers */
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struct pmux_tri_ctlr {
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uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
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uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
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uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
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uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */
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uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */
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uint pmt_tri[PMUX_TRISTATE_REGS];/* _TRI_STATE_REG_A/B/C/D_0 14-20 */
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uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
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uint pmt_reserved[22]; /* ABP_MISC_PP_ reserved offs 28-7C */
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uint pmt_ctl[PMUX_MUX_REGS]; /* _PIN_MUX_CTL_A-G_0, offset 80 */
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uint pmt_reserved4; /* ABP_MISC_PP_ reserved offset 9c */
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uint pmt_pull[PMUX_PULL_REGS]; /* APB_MISC_PP_PULLUPDOWN_REG_A-E */
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};
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/*
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* This defines the configuration for a pin, including the function assigned,
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* pull up/down settings and tristate settings. Having set up one of these
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* you can call pinmux_config_pingroup() to configure a pin in one step. Also
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* available is pinmux_config_table() to configure a list of pins.
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*/
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struct pingroup_config {
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enum pmux_pingrp pingroup; /* pin group PINGRP_... */
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enum pmux_func func; /* function to assign FUNC_... */
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enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
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enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
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};
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/* Set a pin group to tristate */
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void pinmux_tristate_enable(enum pmux_pingrp pin);
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/* Set a pin group to normal (non tristate) */
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void pinmux_tristate_disable(enum pmux_pingrp pin);
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/* Set the pull up/down feature for a pin group */
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void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
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/* Set the mux function for a pin group */
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void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
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/* Set the complete configuration for a pin group */
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void pinmux_config_pingroup(struct pingroup_config *config);
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void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
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/**
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* Configuure a list of pin groups
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*
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* @param config List of config items
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* @param len Number of config items in list
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*/
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void pinmux_config_table(struct pingroup_config *config, int len);
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#endif /* PINMUX_H */
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